Works matching DE "VHDL (Computer hardware description language)"
Results: 118
Hardware implementation of evolutionary algorithms using dynamic reconfiguration technology.
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- Natural Computing, 2015, v. 14, n. 4, p. 593, doi. 10.1007/s11047-014-9476-z
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Development of Library Components for Floating Point Processor.
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- Journal of Ultra Scientist of Physical Sciences - Section A (Mathematics), 2021, v. 33, n. 4, p. 42, doi. 10.22147/jusps-A/330402
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A Review on FPGA Implementation of Distributed Canny Edge Detector.
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- Grenze International Journal of Engineering & Technology (GIJET), 2017, v. 3, n. 3, p. 94
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- Article
IMAGE CONTOUR SEGMENTATION IN HARDWARE.
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- Radio Electronics, Computer Science, Control, 2015, v. 4, p. 66, doi. 10.15588/1607-3274-2015-4-10
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- Article
Microprocessor design using hardware description language.
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- European Journal of Engineering Education, 2008, v. 33, n. 4, p. 425, doi. 10.1080/03043790802253384
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- Article
Improvements in space radiation-tolerant FPGA implementation of land surface temperature-split window algorithm.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2021, v. 11, n. 5, p. 3844, doi. 10.11591/ijece.v11i5.pp3844-3854
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VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2017, v. 7, n. 4, p. 1824, doi. 10.11591/ijece.v7i4.pp1824-1832
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FPGA Based Control Method for Three Phase BLDC Motor.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2016, v. 6, n. 4, p. 1434, doi. 10.11591/ijece.v6i4.10103
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Evaluation of High Speed Hardware Multipliers - Fixed Point and Floating point.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2013, v. 3, n. 6, p. 805, doi. 10.11591/ijece.v3i6.4185
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A Unified Codec Scheme for reduction of Area and Crosstalk in RC and RLC Modeled Interconnects using both Bus Encoding and Shielding Insertion Technique.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2013, v. 3, n. 4, p. 524, doi. 10.11591/ijece.v3i4.3173
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- Article
Relating Event and Trace Semantics of Hardware Description Languages.
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- Computer Journal, 2002, v. 45, n. 1, p. 27, doi. 10.1093/comjnl/45.1.27
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- Article
Synthesizing VHDL from Activity Models in UML 2.
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- International Journal of Circuit Theory & Applications, 2014, v. 42, n. 5, p. 542, doi. 10.1002/cta.1874
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- Article
Unified FPGA Design for the HEVC Dequantization and Inverse Transform Modules.
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- Computers, Materials & Continua, 2022, v. 71, n. 3, p. 4319, doi. 10.32604/cmc.2022.022988
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- Article
Implementation of NonLinear Controller with Anti-Windup on Xilinx FPGA.
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- Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ), 2024, v. 49, n. 9, p. 13005, doi. 10.1007/s13369-024-08912-y
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- Article
Hardware Architecture for the Implementation of the Discrete Wavelet Transform in two Dimensions.
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- Ingeniería y Competitividad, 2014, v. 16, n. 1, p. 69
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- Article
Integrated classifier simulator and neurochip VHDL implementation.
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- International Journal of Computer Mathematics, 2003, v. 80, n. 11, p. 1343, doi. 10.1080/0020716031000148223
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Invariant-Based Safety Assessment of FPGA Projects: Conception and Technique.
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- Computers (2073-431X), 2021, v. 10, n. 10, p. 125, doi. 10.3390/computers10100125
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- Article
A Reconfigurable Hybrid Architecture for HomePNA3.1/Ethernet MAC.
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- Majlesi Journal of Electrical Engineering, 2011, v. 5, n. 4, p. 46
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- Article
Performance Evaluation of Squaring Operation by Vedic Mathematics.
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- IETE Journal of Research, 2011, v. 57, n. 1, p. 39, doi. 10.4103/0377-2063.78327
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Teaching hardware description languages to satisfy industry expectations.
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- International Journal of Electrical Engineering Education, 2009, v. 46, n. 3, p. 239, doi. 10.7227/IJEEE.46.3.3
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- Article
Instructional tools for designing and analysing a very simple CPU.
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- International Journal of Electrical Engineering Education, 2006, v. 43, n. 3, p. 261, doi. 10.7227/IJEEE.43.3.7
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- Article
A virtual interactive teaching environment using XML and augmented reality.
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- International Journal of Electrical Engineering Education, 2001, v. 38, n. 4, p. 316, doi. 10.7227/IJEEE.38.4.5
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- Article
Efficient Hardware Implementations for Tripling Oriented Elliptic Curve Crypto-System.
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- International Review on Computers & Software, 2014, v. 9, n. 4, p. 609
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- Article
A novel design of variable-rate RS encoder for ubiquitous high performance multimedia service in Gbps transmission system.
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- Journal of Supercomputing, 2011, v. 55, n. 2, p. 192, doi. 10.1007/s11227-010-0441-z
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- Article
SEU Fault-Injection in VHDL-Based Processors: A Case Study.
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- Journal of Electronic Testing, 2013, v. 29, n. 1, p. 87, doi. 10.1007/s10836-013-5351-6
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- Article
Performance evaluation of a new efficient H.264 intraprediction scheme.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2016, v. 24, n. 3, p. 1967, doi. 10.3906/elk-1312-250
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- Article
Implementación del algoritmo Threefish-256 en hardware reconfigurable.
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- Iteckne, 2014, v. 11, n. 2, p. 149, doi. 10.15332/iteckne.v11i2.725
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Synthesis and implementation of the ordered access memory in programmable logic devices.
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- Metallurgical & Mining Industry, 2016, n. 4, p. 58
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NSL: A Neuro–Symbolic Language for a Neuro–Symbolic Processor (NSP).
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- International Journal of Neural Systems, 2003, v. 13, n. 2, p. 93, doi. 10.1142/S0129065703001480
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- Article
Implementation of a Pulse Coupled Neural Network in FPGA.
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- International Journal of Neural Systems, 2000, v. 10, n. 3, p. 171, doi. 10.1142/S0129065700000156
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VHDL Descriptions for the FPGA Implementation of PWL-Function-Based Multi-Scroll Chaotic Oscillators.
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- PLoS ONE, 2016, v. 11, n. 12, p. 1, doi. 10.1371/journal.pone.0168300
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Analysis and Performance Evaluation of PD-like Fuzzy Logic Controller Design Based on Matlab and FPGA.
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- IAENG International Journal of Computer Science, 2010, v. 37, n. 2, p. 146
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Project verification and construction of superchip tests at the RTL level.
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- Automation & Remote Control, 2013, v. 74, n. 1, p. 113, doi. 10.1134/S0005117913010104
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Development of tests for VLSI circuit testability at the upper design levels.
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- Automation & Remote Control, 2010, v. 71, n. 9, p. 1888, doi. 10.1134/S0005117910090110
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- Article
Design of 4 bits Combinational Lock Using VHDL.
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- International Journal of Electrical, Electronics & Computer Systems, 2014, v. 19, n. 2, p. 15
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Simulating the effects of logic faults in implementation-level VITAL-compliant models.
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- Computing, 2019, v. 101, n. 2, p. 77, doi. 10.1007/s00607-018-0651-4
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- Article
Property-Model Methodology: A Model-Based Systems Engineering Approach Using VHDL-AMS.
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- Systems Engineering, 2014, v. 17, n. 3, p. 249, doi. 10.1002/sys.21267
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- Article
Development of IEEE-754 to Decimal Conversion of Library Components for Floating Point Arithmetic Logic Unit.
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- International Transactions in Mathematical Sciences & Computer, 2011, v. 4, n. 2, p. 165
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- Article
Cardiac Arrhythmias Detection by Neural Networks: VHDL Modeling and Synthesis on FPGA.
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- International Review of Automatic Control, 2012, v. 5, n. 5, p. 689
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- Article
Modeling and Implementation of a Power Estimation Methodology for SystemC.
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- International Journal of Reconfigurable Computing, 2012, p. 1, doi. 10.1155/2012/439727
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- Article
A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos.
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- International Journal of Reconfigurable Computing, 2011, p. 1, doi. 10.1155/2011/254730
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- Article
vMAGIC--Automatic Code Generation for VHDL.
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- International Journal of Reconfigurable Computing, 2009, p. 1, doi. 10.1155/2009/205149
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- Article
Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System.
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- International Journal of Reconfigurable Computing, 2008, p. 1, doi. 10.1155/2008/634306
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- Article
Accurate Model for Network-on-Chip Performance Evaluation Based on Timed Colored Petri Net.
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- Journal of Integrated Circuits & Systems, 2016, v. 11, n. 2, p. 75, doi. 10.29292/jics.v11i2.432
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- Article
Fast Processing of Non-Repeated Values in Hardware.
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- Electronics & Electrical Engineering, 2017, v. 23, n. 3, p. 74, doi. 10.5755/j01.eie.23.3.18336
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- Article
Generic FPGA Pre-Processing Image Library for Industrial Vision Systems.
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- Sensors (14248220), 2024, v. 24, n. 18, p. 6101, doi. 10.3390/s24186101
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- Article
A Multifunctional Smart Meter Using ANN-PSO Flux Estimation and Harmonic Active Compensation with Fuzzy Voltage Regulation.
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- Sensors (14248220), 2021, v. 21, n. 12, p. 4154, doi. 10.3390/s21124154
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- Article
Quantitative comparison of performance analysis techniques for modular and generic network-on-chip.
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- Advances in Radio Science, 2009, v. 7, p. 107, doi. 10.5194/ars-7-107-2009
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- Article
Decodificador Turbo MAP de varias iteraciones.
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- Ingeniería y Desarrollo, 2006, n. 20, p. 106
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- Article
Software tool for efficient FPGA design of direct data domain approach for space-time adaptive processing.
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- Electronics Letters (Wiley-Blackwell), 2013, v. 49, n. 13, p. 1, doi. 10.1049/el.2013.1307
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- Article