Works matching DE "FIELD programmable analog arrays"
Results: 110
The Implementation of an Amplitude-Locked Loop for Digital Communication Chip Design.
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- Wireless Personal Communications, 2013, v. 72, n. 4, p. 2773, doi. 10.1007/s11277-013-1180-2
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On-the-fly Computation Method in Field-Programmable Gate Array for Analog-to-Digital Converter Linearity Testing.
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- Journal of Engineering & Technological Sciences, 2018, v. 50, n. 5, p. 589, doi. 10.5614/j.eng.technol.sci.2018.50.5.1
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Extrema-Triggered Conversion for Non-Stationary Signal Acquisition in Wireless Sensor Nodes.
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- Journal of Low Power Electronics & Applications, 2024, v. 14, n. 1, p. 11, doi. 10.3390/jlpea14010011
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Analog System High-Level Synthesis for Energy-Efficient Reconfigurable Computing.
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- Journal of Low Power Electronics & Applications, 2023, v. 13, n. 4, p. 58, doi. 10.3390/jlpea13040058
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The Potential of SoC FPAAs for Emerging Ultra-Low-Power Machine Learning.
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- Journal of Low Power Electronics & Applications, 2022, v. 12, n. 2, p. 33, doi. 10.3390/jlpea12020033
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An Acoustic Vehicle Detector and Classifier Using a Reconfigurable Analog/Mixed-Signal Platform.
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- Journal of Low Power Electronics & Applications, 2020, v. 10, n. 1, p. 6, doi. 10.3390/jlpea10010006
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Security Implications for Ultra-Low Power Configurable SoC FPAA Embedded Systems.
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- Journal of Low Power Electronics & Applications, 2018, v. 8, n. 2, p. 17, doi. 10.3390/jlpea8020017
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Models and Techniques for Temperature Robust Systems on a Reconfigurable Platform.
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- Journal of Low Power Electronics & Applications, 2017, v. 7, n. 3, p. 21, doi. 10.3390/jlpea7030021
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Starting Framework for Analog Numerical Analysis for Energy-Efficient Computing.
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- Journal of Low Power Electronics & Applications, 2017, v. 7, n. 3, p. 17, doi. 10.3390/jlpea7030017
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Remote System Setup Using Large-Scale Field Programmable Analog Arrays (FPAA) to Enabling Wide Accessibility of Configurable Devices.
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- Journal of Low Power Electronics & Applications, 2016, v. 6, n. 3, p. 14, doi. 10.3390/jlpea6030014
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Scaling Floating-Gate Devices Predicting Behavior for Programmable and Configurable Circuits and Systems.
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- Journal of Low Power Electronics & Applications, 2016, v. 6, n. 3, p. 13, doi. 10.3390/jlpea6030013
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- Article
FPGA-Based Design of an Intelligent On-Chip Sensor Network Monitoring and Control Using Dynamically Reconfigurable Autonomous Sensor Agents.
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- International Journal of Distributed Sensor Networks, 2016, p. 1, doi. 10.1155/2016/4246596
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- Article
Resistorless Reconfigurable nth-Order Filter Based on DPCDTA for Multi-mode Filtering Applications.
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- Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ), 2015, v. 40, n. 8, p. 2423, doi. 10.1007/s13369-015-1717-7
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On Chip Pulse Width Modulator and Dead Time Controller in Bidirectional DC to DC Converter for Aero Space Applications.
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- Arabian Journal for Science & Engineering (Springer Science & Business Media B.V. ), 2014, v. 39, n. 2, p. 957, doi. 10.1007/s13369-013-0683-1
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Mutation Testing for Effective Verification of Digital Components of Physical Systems.
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- Russian Physics Journal, 2015, v. 58, n. 8, p. 1128, doi. 10.1007/s11182-015-0622-6
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Implementación de Osciladores Caóticos Autónomos basada en Op Amps y FPAA.
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- Revista Internacional de Tecnología, Conocimiento y Sociedad, 2022, v. 10, n. 1, p. 1, doi. 10.18848/2474-588X/CGP/v10i01/1-12
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- Article
Memcapacitor emulator based on the Miller effect.
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- International Journal of Circuit Theory & Applications, 2019, v. 47, n. 4, p. 572, doi. 10.1002/cta.2604
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FPGA implementation of adaptive time delay estimation for real‐time near‐field electromagnetic ranging.
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- International Journal of Circuit Theory & Applications, 2018, v. 46, n. 11, p. 1940, doi. 10.1002/cta.2513
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A low‐power digital IC emulating intracellular calcium dynamics.
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- International Journal of Circuit Theory & Applications, 2018, v. 46, n. 11, p. 1929, doi. 10.1002/cta.2514
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- Article
Asynchronous delay doubler and binary low-pass filter for a time-delay chaotic circuit.
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- International Journal of Circuit Theory & Applications, 2016, v. 44, n. 6, p. 1211, doi. 10.1002/cta.2158
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- Article
Digitally programmable second generation current conveyor-based FPAA.
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- International Journal of Circuit Theory & Applications, 2013, v. 41, n. 10, p. 1074, doi. 10.1002/cta.1826
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Design and implementation of a digitally controlled single-inductor dual-output (SIDO) buck converter.
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- International Journal of Circuit Theory & Applications, 2014, v. 42, n. 3, p. 221, doi. 10.1002/cta.1844
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- Article
Design and Implementation Model for Linearization Sensor Characteristic by FPAA.
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- Iraqi Journal for Electrical & Electronic Engineering, 2015, v. 11, n. 2, p. 165, doi. 10.33762/eeej.2015.106238
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- Article
High-Bandwidth, Low-Power CMOS Transistor Based CAB for Field Programmable Analog Array.
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- Computers, Materials & Continua, 2023, v. 74, n. 3, p. 5885, doi. 10.32604/cmc.2023.033789
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An Ultra-fast DOA Estimator with Circular Array Interferometer Using Lookup Table Method.
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- Radioengineering, 2015, v. 24, n. 3, p. 850, doi. 10.13164/re.2015.0850
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COMPUTER AIDED DESIGN OF SINGLE-ELECTRON NANOCIRCUITS.
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- Electronics & Control Systems, 2013, v. 3, n. 37, p. 71
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FPGA Based Real-Time Emulation System for Power Electronics Converters.
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- Energies (19961073), 2019, v. 12, n. 6, p. 969, doi. 10.3390/en12060969
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A Novel FPGA-Based Real-Time Simulator for Micro-Grids.
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- Energies (19961073), 2017, v. 10, n. 8, p. 1239, doi. 10.3390/en10081239
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FPGA Implementation of a Binarized Dual Stream Convolutional Neural Network for Service Robots.
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- Journal of Robotics & Mechatronics, 2021, v. 33, n. 2, p. 386, doi. 10.20965/jrm.2021.p0386
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Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs.
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- Information Security Journal: A Global Perspective, 2013, v. 22, n. 5/6, p. 265, doi. 10.1080/19393555.2014.891281
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Fpaa-Based Virtual Instrumentation Laboratory With Remote Access.
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- Webology, 2022, v. 19, n. 6, p. 847
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Fpaa-Based Virtual Instrumentation Laboratory With Remote Access.
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- Webology, 2022, v. 19, n. 4, p. 447
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Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA.
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- IET Computers & Digital Techniques (Wiley-Blackwell), 2021, v. 15, n. 5, p. 362, doi. 10.1049/cdt2.12028
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- Article
Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA.
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- IET Computers & Digital Techniques (Wiley-Blackwell), 2021, v. 15, n. 5, p. 349, doi. 10.1049/cdt2.12027
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A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance.
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- International Journal of Reconfigurable Computing, 2017, p. 1, doi. 10.1155/2017/5419767
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TreeBASIS Feature Descriptor and Its Hardware Implementation.
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- International Journal of Reconfigurable Computing, 2014, p. 1, doi. 10.1155/2014/606210
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- Article
FFT Splitting for Improved FPGA-Based Acquisition of GNSS Signals.
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- International Journal of Navigation & Observation, 2015, p. 1, doi. 10.1155/2015/765898
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- Article
A Damping-Tunable Snap System: From Dissipative Hyperchaos to Conservative Chaos.
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- Entropy, 2022, v. 24, n. 1, p. 121, doi. 10.3390/e24010121
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- Article
Design and Implementation of Autonomous and Non-Autonomous Time-Delay Chaotic System Based on Field Programmable Analog Array.
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- Entropy, 2019, v. 21, n. 5, p. 437, doi. 10.3390/e21050437
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- Article
On-line experiments on rapid detection of radionuclides based on sequential Bayesian analysis.
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- Journal of Radioanalytical & Nuclear Chemistry, 2015, v. 306, n. 1, p. 57, doi. 10.1007/s10967-015-4072-y
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- Article
Realization of fractional band pass filter on reconfigurable analog device.
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- International Review of Applied Sciences & Engineering, 2022, v. 13, n. 3, p. 63, doi. 10.1556/1848.2021.00308
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- Article
Realization of fractional band pass filter on reconfigurable analog device.
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- International Review of Applied Sciences & Engineering, 2021, v. 13, n. 1, p. 63, doi. 10.1556/1848.2021.00308
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- Article
THREE-DIMENSIONAL ARTIFICIAL ORGANISM MODEL DEVELOPED UPON A TWO-LAYER COARSE-FINE-GRID NETWORK APPROACH.
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- International Review of Applied Sciences & Engineering, 2017, v. 8, n. 2, p. 127, doi. 10.1556/1848.2017.8.2.4
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- Article
An Analog MP3 Compression Psychoacoustic Model Implemented on a Field-Programmable Analog Array.
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- Electronics (2079-9292), 2024, v. 13, n. 14, p. 2691, doi. 10.3390/electronics13142691
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A Study on Fractional Power-Law Applications and Approximations.
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- Electronics (2079-9292), 2024, v. 13, n. 3, p. 591, doi. 10.3390/electronics13030591
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Power-Law Negative Group Delay Filters.
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- Electronics (2079-9292), 2024, v. 13, n. 3, p. 522, doi. 10.3390/electronics13030522
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Field Programmable Analog Array Based Non-Integer Filter Designs.
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- Electronics (2079-9292), 2023, v. 12, n. 16, p. 3427, doi. 10.3390/electronics12163427
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A 1 + α Order Generalized Butterworth Filter Structure and Its Field Programmable Analog Array Implementation.
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- Electronics (2079-9292), 2023, v. 12, n. 5, p. 1225, doi. 10.3390/electronics12051225
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Versatile Field-Programmable Analog Array Realizations of Power-Law Filters.
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- Electronics (2079-9292), 2022, v. 11, n. 5, p. 692, doi. 10.3390/electronics11050692
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Power-Law Compensator Design for Plants with Uncertainties: Experimental Verification.
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- Electronics (2079-9292), 2021, v. 10, n. 11, p. 1305, doi. 10.3390/electronics10111305
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