Works matching DE "MICROPROCESSORS"

Results: 1535

The Microprocessor controls the activity of mammalian retrotransposons.

Published in:

Nature Structural & Molecular Biology, 2013, v. 20, n. 10, p. 1173, doi. 10.1038/nsmb.2658

By:

Heras, Sara R;
Macias, Sara;
Plass, Mireya;
Fernandez, Noemí;
Cano, David;
Eyras, Eduardo;
Garcia-Perez, José L;
Cáceres, Javier F

Publication type:

Article

DGCR8 HITS-CLIP reveals novel functions for the Microprocessor.

Published in:

Nature Structural & Molecular Biology, 2012, v. 19, n. 8, p. 760, doi. 10.1038/nsmb.2344

By:

Macias, Sara;
Plass, Mireya;
Stajuda, Agata;
Michlewski, Gracjan;
Eyras, Eduardo;
Cáceres, Javier F

Publication type:

Article

Motion control brings design relief.

Published in:

Power Engineer, 2004, v. 18, n. 1, p. 38, doi. 10.1049/pe:20040110

By:

Takahashi, Toshio

Publication type:

Article

A fast sample entropy for pulse rate variability analysis.

Published in:

Medical & Biological Engineering & Computing, 2023, v. 61, n. 7, p. 1603, doi. 10.1007/s11517-022-02766-y

By:

Chou, Lijuan;
Gong, Shengrong;
Yang, Haiping;
Liu, Jicheng;
Chou, Yongxin

Publication type:

Article

Advances in Precise Structure Control and Assembly toward the Carbon Nanotube Industry.

Published in:

Advanced Functional Materials, 2022, v. 32, n. 11, p. 1, doi. 10.1002/adfm.202109401

By:

Zhu, Zhenxing;
Cui, Chaojie;
Bai, Yunxiang;
Gao, Jun;
Jiang, Yaxin;
Li, Bofan;
Wang, Yao;
Zhang, Qiang;
Qian, Weizhong;
Wei, Fei

Publication type:

Article

Thermal error compensation method for machine center.

Published in:

International Journal of Advanced Manufacturing Technology, 2012, v. 59, n. 5-8, p. 681, doi. 10.1007/s00170-011-3533-x

By:

Wu, Ching-Wei;
Tang, Chia-Hui;
Chang, Ching-Feng;
Shiao, Ying-Shing

Publication type:

Article

A study on the generation of silicon-based hardware Plc by means of the direct conversion of the ladder diagram to circuit design language.

Published in:

International Journal of Advanced Manufacturing Technology, 2010, v. 49, n. 5-8, p. 615, doi. 10.1007/s00170-009-2405-0

By:

Daoshan Du;
Xiaodong Xu;
Yamazaki, Kazuo

Publication type:

Article

Study on LD-VHDL conversion for FPGA-based PLC implementation.

Published in:

International Journal of Advanced Manufacturing Technology, 2009, v. 40, n. 11/12, p. 1181, doi. 10.1007/s00170-008-1426-4

By:

Daoshan Du;
Yadong Liu;
Xingui Guo;
Yamazaki, Kazuo;
Fujishima, Makoto

Publication type:

Article

FPGA based failure monitoring system for machining processes.

Published in:

International Journal of Advanced Manufacturing Technology, 2009, v. 40, n. 7/8, p. 676, doi. 10.1007/s00170-008-1386-8

By:

Franco-Gasca, Luis;
Jesús Romero-Troncoso, René;
Herrera-Ruiz, Gilberto;
Rocío Peniche-Vera, Rebeca

Publication type:

Article

Tool condition monitoring in an end-milling operation based on the vibration signal collected through a microcontroller-based data acquisition system.

Published in:

International Journal of Advanced Manufacturing Technology, 2008, v. 39, n. 1/2, p. 118, doi. 10.1007/s00170-007-1186-6

By:

Zhang, Julie;
Chen, Joseph

Publication type:

Article

The design of a single-chip tool monitoring system for on-line turning operation.

Published in:

International Journal of Advanced Manufacturing Technology, 2004, v. 24, n. 5/6, p. 404, doi. 10.1007/s00170-003-1780-1

By:

Tseng, P.-C.;
Teng, W.-C.

Publication type:

Article

Analysis of Low Power Consumption Techniques on FPGA for Wireless Devices.

Published in:

Wireless Personal Communications, 2017, v. 95, n. 2, p. 353, doi. 10.1007/s11277-016-3896-2

By:

Verma, Gaurav;
Kumar, Manish;
Khare, Vijay;
Pandey, Bishwajeet

Publication type:

Article

Q&A: Taking charge.

Published in:

2012

By:

Palacios, Tomás

Publication type:

Interview

Management of Hardware Vulnerabilities in the Life Cycle Stages of Microprocessors and Computers.

Published in:

Inventions (2411-5134), 2023, v. 8, n. 4, p. 98, doi. 10.3390/inventions8040098

By:

Bychkov, Ignat;
Mikhailova, Irina;
Korenev, Pavel;
Pikov, Vitaliy;
Ryapukhin, Anatoly

Publication type:

Article

异构多核SoC处理器内部存储架构优化.

Published in:

Electronic Science & Technology, 2022, v. 35, n. 9, p. 44, doi. 10.16180/j.cnki.issn1007-7820.2022.09.007

By:

张玄;
张多利;
宋宇鲲

Publication type:

Article

Methods of Improving Technical and Functional Characteristics of Serial Budget Microprocessor Platforms.

Published in:

Journal Européen des Systèmes Automatisés, 2022, v. 55, n. 1, p. 81, doi. 10.18280/jesa.550108

By:

Lebediev, Vladyslav A.;
Laktionov, Ivan S.;
Vovna, Oleksandr V.;
Kabanets, Maryna M.;
Sahaida, Pavlo I.;
Dobrovolska, Liudmyla O.

Publication type:

Article

The C-Brace® microprocessor controlled stance and swing orthosis improves safety, mobility, and quality of life at one year: Interim results from a prospective registry.

Published in:

Journal of Rehabilitation & Assistive Technologies Engineering, 2024, p. 1, doi. 10.1177/20556683241269539

By:

Lundstrom, Russell L;
Klenow, Tyler D;
Morris, Arri;
Pobatschnig, Barbara;
Hibler, Karl D;
Kannenberg, Andreas HJ

Publication type:

Article

Microprocessor feet improve prosthetic mobility and physical function relative to non-microprocessor feet.

Published in:

Journal of Rehabilitation & Assistive Technologies Engineering, 2022, p. 1, doi. 10.1177/20556683221113320

By:

Weber, Eric L;
Stevens, Phillip M;
England, Dwiesha L;
Swilley, Vahness D;
Wurdeman, Shane R

Publication type:

Article

Microprocessor feet improve prosthetic mobility and physical function relative to non-microprocessor feet.

Published in:

Journal of Rehabilitation & Assistive Technologies Engineering, 2022, v. 9, p. 1, doi. 10.1177/20556683221113320

By:

Weber, Eric L.;
Stevens, Phillip M.;
England, Dwiesha L.;
Swilley, Vahness D.;
Wurdeman, Shane R.

Publication type:

Article

Response to: Letter to editor regarding: OASIS 1: Retrospective analysis of four different microprocessor knee types by Campbell et al.

Published in:

Journal of Rehabilitation & Assistive Technologies Engineering, 2021, v. 8, p. 1, doi. 10.1177/20556683211022232

By:

Campbell, James H.;
Stevens, Phillip M.;
Wurdeman, Shane R.

Publication type:

Article

Analysis of Inadvertent Microprocessor Lag Time on Eddy Covariance Results.

Published in:

Journal of Applied Meteorology (1988), 2001, v. 40, n. 9, doi. 10.1175/1520-0450(2001)040<1640:AOIMLT>2.0.CO;2

By:

Zeller, Karl;
Zimmerman, Gary;
Hehn, Ted;
Donev, Evgeny;
Denny, Diane;
Welker, Jeff

Publication type:

Article

In situ monitoring of ultrasonic welding of thermoplastic composites through power and displacement data.

Published in:

Journal of Thermoplastic Composite Materials, 2015, v. 28, n. 1, p. 66, doi. 10.1177/0892705712475015

By:

Villegas, Irene Fernandez

Publication type:

Article

Editorial: Special Issue on Side-Channel and Fault Analysis of High-Performance Computing Platforms.

Published in:

2019

By:

Ghalaty, Nahid Farhady

Publication type:

Editorial

Variable Length Instruction Compression on Transport Triggered Architectures.

Published in:

International Journal of Parallel Programming, 2018, v. 46, n. 6, p. 1283, doi. 10.1007/s10766-018-0568-8

By:

Viitanen, Timo;
Kultala, Heikki;
Jääskeläinen, Pekka;
Takala, Jarmo;
Helkala, Janne;
Zetterman, Tommi;
Berg, Heikki

Publication type:

Article

Microcode Compression Using Structured-Constrained Clustering.

Published in:

International Journal of Parallel Programming, 2014, v. 42, n. 1, p. 140, doi. 10.1007/s10766-012-0206-9

By:

Borin, Edson;
Araujo, Guido;
Breternitz, Mauricio;
Wu, Youfeng

Publication type:

Article

ADL-Based Specification of Implementation Styles for Functional Simulators.

Published in:

International Journal of Parallel Programming, 2013, v. 41, n. 2, p. 163, doi. 10.1007/s10766-012-0223-8

By:

Penry, David;
Cahill, Kurtis

Publication type:

Article

The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic Adaptation.

Published in:

International Journal of Parallel Programming, 2013, v. 41, n. 2, p. 305, doi. 10.1007/s10766-012-0220-y

By:

Sundararajan, Karthik;
Jones, Timothy;
Topham, Nigel

Publication type:

Article

Combining Height Reduction and Scheduling for VLIW Machines Enhanced with Three-Argument Arithmetic Operations.

Published in:

International Journal of Parallel Programming, 2012, v. 40, n. 5, p. 488, doi. 10.1007/s10766-012-0196-7

By:

Abboud, Fadi;
Ben-Asher, Yosi;
Shajrawi, Yousef;
Stein, Esti

Publication type:

Article

Managing Data Placement in Memory Systems with Multiple Memory Controllers.

Published in:

International Journal of Parallel Programming, 2012, v. 40, n. 1, p. 57, doi. 10.1007/s10766-011-0178-1

By:

Awasthi, M.;
Nellans, D.;
Sudan, K.;
Balasubramonian, R.;
Davis, A.

Publication type:

Article

Parallel Implementation of 2-D Telegraphic Equation on MPI/PVM Cluster.

Published in:

International Journal of Parallel Programming, 2011, v. 39, n. 2, p. 202, doi. 10.1007/s10766-010-0148-z

By:

Ewedafe, Simon;
Shariffudin, Rio

Publication type:

Article

A Dynamic Load Balancing Framework for Real-time Applications in Message Passing Systems.

Published in:

International Journal of Parallel Programming, 2011, v. 39, n. 2, p. 143, doi. 10.1007/s10766-010-0134-5

By:

El Kabbany, Ghada;
Wanas, Nayer;
Hegazi, Nadia;
Shaheen, Samir

Publication type:

Article

Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration.

Published in:

International Journal of Parallel Programming, 2010, v. 38, n. 3/4, p. 203, doi. 10.1007/s10766-010-0128-3

By:

Suri, Tameesh;
Aggarwal, Aneesh

Publication type:

Article

Tolerating Radiation-Induced Transient Faults in Modern Processors.

Published in:

International Journal of Parallel Programming, 2010, v. 38, n. 2, p. 85, doi. 10.1007/s10766-009-0114-9

By:

Li, Xiaobin;
Gaudiot, Jean-Luc

Publication type:

Article

Computing Optimised Parallel Speeded-Up Robust Features (P-SURF) on Multi-Core Processors.

Published in:

International Journal of Parallel Programming, 2010, v. 38, n. 2, p. 138, doi. 10.1007/s10766-009-0122-9

By:

Zhang, Nan

Publication type:

Article

New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components.

Published in:

International Journal of Parallel Programming, 2009, v. 37, n. 4, p. 417, doi. 10.1007/s10766-009-0104-y

By:

DeBole, Michael;
Krishnan, Ramakrishnan;
Balakrishnan, Varsha;
Wenping Wang;
Hong Luo;
Yu Wang;
Yuan Xie;
Yu Cao;
Vijaykrishnan, N.

Publication type:

Article

Performance Advantage of Reconfigurable Cache Design on Multicore Processor Systems.

Published in:

International Journal of Parallel Programming, 2008, v. 36, n. 3, p. 347, doi. 10.1007/s10766-008-0075-4

By:

Jie Tao;
Kunze, Marcel;
Nowak, Fabian;
Buchty, Rainer;
Karl, Wolfgang

Publication type:

Article

Supporting OpenMP on Cell.

Published in:

International Journal of Parallel Programming, 2008, v. 36, n. 3, p. 289, doi. 10.1007/s10766-008-0072-7

By:

O'Brien, Kevin;
O'Brien, Kathryn;
Sura, Zehra;
Tong Chen;
Tao Zhang

Publication type:

Article

Dynamic Instruction Scheduling in a Trace-based Multi-threaded Architecture.

Published in:

International Journal of Parallel Programming, 2008, v. 36, n. 2, p. 184, doi. 10.1007/s10766-007-0062-1

By:

Rounce, Peter A.;
Souza, Alberto F.

Publication type:

Article

Analyzing the Effects of Hyperthreading on the Performance of Data Management Systems.

Published in:

International Journal of Parallel Programming, 2008, v. 36, n. 2, p. 206, doi. 10.1007/s10766-007-0066-x

By:

Hassanein, Wessam;
Rashid, Layali;
Hammad, Moustafa

Publication type:

Article

Modulo Path History for the Reduction of Pipeline Overheads in Path-based Neural Branch Predictors.

Published in:

International Journal of Parallel Programming, 2008, v. 36, n. 2, p. 267, doi. 10.1007/s10766-007-0063-0

By:

Loh, Gabriel;
Jiménez, Daniel

Publication type:

Article

Dynamic Data Migration for Structured AMR Solvers.

Published in:

International Journal of Parallel Programming, 2007, v. 35, n. 5, p. 477, doi. 10.1007/s10766-007-0056-z

By:

Nordén, Markus;
Löf, Henrik;
Rantakokko, Jarmo;
Holmgren, Sverker

Publication type:

Article

Scientific Computing Kernels on the Cell Processor.

Published in:

International Journal of Parallel Programming, 2007, v. 35, n. 3, p. 263, doi. 10.1007/s10766-007-0034-5

By:

Williams, Samuel;
Shalf, John;
Oliker, Leonid;
Kamil, Shoaib;
Husbands, Parry;
Yelick, Katherine

Publication type:

Article

FEADS: A Framework for Exploring the Application Design Space on Network Processors.

Published in:

International Journal of Parallel Programming, 2007, v. 35, n. 1, p. 1, doi. 10.1007/s10766-006-0023-0

By:

Pai, Rajani;
Govindarajan, R.

Publication type:

Article

A Case for Chip Multiprocessors Based on the Data-Driven Multithreading Model.

Published in:

International Journal of Parallel Programming, 2006, v. 34, n. 3, p. 213, doi. 10.1007/s10766-006-0016-z

By:

Trancoso, Pedro;
Evripidou, Paraskevas;
Stavrou, Kyriakos;
Kyriacou, Costas

Publication type:

Article

Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References.

Published in:

International Journal of Parallel Programming, 2005, v. 33, n. 5, p. 529, doi. 10.1007/s10766-005-7304-x

By:

Mutlu, Onur;
Kim, Hyesoon;
Armstrong, David;
Patt, Yale

Publication type:

Article

SMA: A Self-Monitored Adaptive Cache Warm-Up Scheme for Microprocessor Simulation.

Published in:

International Journal of Parallel Programming, 2005, v. 33, n. 5, p. 561, doi. 10.1007/s10766-005-7305-9

By:

Luo, Yue;
John, Lizy;
Eeckhout, Lieven

Publication type:

Article

Register Saturation in Instruction Level Parallelism.

Published in:

International Journal of Parallel Programming, 2005, v. 33, n. 4, p. 393, doi. 10.1007/s10766-005-6466-x

By:

Touati, Sid-Ahmed-Ali

Publication type:

Article

Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures.

Published in:

International Journal of Parallel Programming, 2004, v. 32, n. 6, p. 447, doi. 10.1023/B:IJPP.0000042082.31819.6d

By:

Zalamea, Javier;
Llosa, Josep;
Ayguadé, Eduard;
Valero, Mateo

Publication type:

Article

Page Migration with Dynamic Space-Sharing Scheduling Policies: The Case of the SGI O2000.

Published in:

International Journal of Parallel Programming, 2004, v. 32, n. 4, p. 263, doi. 10.1023/B:IJPP.0000035815.13969.ec

By:

Corbalan, Julita;
Martorell, Xavier;
Labarta, Jesus

Publication type:

Article

Dynamic Memory Instruction Bypassing.

Published in:

International Journal of Parallel Programming, 2004, v. 32, n. 3, p. 199, doi. 10.1023/B:IJPP.0000029273.49634.19

By:

Ortega, Daniel;
Valero, Mateo;
Ayguadé, Eduard

Publication type:

Article