High Speed and Efficient Wallace Tree Multiplier for Dsp Applications.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2020, v. 2, n. 1, p. 1, doi. 10.31838/jvcs/02.01.01
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- Publication type:
- Article
Works matching DE "MULTIPLYING circuits"
Results: 13
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Efficient hardware implementations of point multiplication for binary Edwards curves.
- Published in:
- International Journal of Circuit Theory & Applications, 2018, v. 46, n. 8, p. 1516, doi. 10.1002/cta.2498
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- Publication type:
- Article
3
Simplified carry save adder-based array multiplier scheme and circuits design.
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- International Journal of Circuit Theory & Applications, 2015, v. 43, n. 9, p. 1226, doi. 10.1002/cta.1998
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- Article
4
Compact power divider for wideband in-phase and out-of-phase performances using parallel coupled lines.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2017, v. 53, n. 19, p. 27, doi. 10.1049/el.2017.2289
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- Publication type:
- Article
5
Parallel in/out systolic AB² architecture with low complexity in GF(2<sup>m</sup>).
- Published in:
- Electronics Letters (Wiley-Blackwell), 2016, v. 52, n. 13, p. 1138, doi. 10.1049/el.2015.3681
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- Article
6
W-band dual-channel receiver with active power divider and temperaturecompensated circuit.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2016, v. 52, n. 10, p. 850, doi. 10.1049/el.2015.3781
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- Publication type:
- Article
7
Analogue multiplier using passive circuits and digital primitives with time-mode signal representation.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2015, v. 51, n. 22, p. 1754, doi. 10.1049/el.2015.2235
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- Publication type:
- Article
8
9 bit superconductive single-flux-quantum digital-to-analogue converter.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2014, v. 50, n. 22, p. 1637, doi. 10.1049/el.2014.1926
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- Publication type:
- Article
9
Design of Low-Voltage and Low-Power DTMOS Based Analog Multiplier Utilizing Current Squarer.
- Published in:
- International Journal of Electronics Letters, 2021, v. 9, n. 1, p. 1, doi. 10.1080/21681724.2021.1889041
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- Publication type:
- Article
10
Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier.
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- Journal of Supercomputing, 2016, v. 72, n. 4, p. 1477, doi. 10.1007/s11227-016-1676-0
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- Publication type:
- Article
11
Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization.
- Published in:
- Wireless Personal Communications, 2018, v. 98, n. 4, p. 3549, doi. 10.1007/s11277-017-5028-z
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- Article
12
A Modified Low Power FFT/IFFT Processor for OFDM Applications.
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- International Journal of Advanced Research in Computer Science, 2013, v. 4, n. 2, p. 362
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- Publication type:
- Article
13
High-selectivity dual-band filtering power divider using stub-loaded quarter-wavelength resonator.
- Published in:
- Journal of Electromagnetic Waves & Applications, 2015, v. 29, n. 16, p. 2216, doi. 10.1080/09205071.2015.1088405
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- Publication type:
- Article