Works matching IS 09238174 AND DT 2016 AND VI 32 AND IP 5
Results: 12
A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 5, p. 611, doi. 10.1007/s10836-016-5598-9
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- Publication type:
- Article
Reliability Analysis of Fault-Tolerant Bus-Based Interconnection Networks.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 5, p. 541, doi. 10.1007/s10836-016-5601-5
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- Publication type:
- Article
Optimization of Test Wrapper for TSV Based 3D SOCs.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 5, p. 511, doi. 10.1007/s10836-016-5610-4
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- Publication type:
- Article
A Novel Approach for Diagnosis of Analog Circuit Fault by Using GMKL-SVM and PSO.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 5, p. 531, doi. 10.1007/s10836-016-5616-y
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- Publication type:
- Article
Test Technology Newsletter.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 5, p. 507, doi. 10.1007/s10836-016-5612-2
- Publication type:
- Article
A Novel Compact Model for On-Chip Vertically-Coiled Spiral Inductors.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 5, p. 649, doi. 10.1007/s10836-016-5613-1
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- Publication type:
- Article
Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 5, p. 601, doi. 10.1007/s10836-016-5614-0
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- Publication type:
- Article
CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 5, p. 625, doi. 10.1007/s10836-016-5615-z
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- Publication type:
- Article
Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 5, p. 587, doi. 10.1007/s10836-016-5611-3
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- Publication type:
- Article
Editorial.
- Published in:
- 2016
- By:
- Publication type:
- Editorial
Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 5, p. 569, doi. 10.1007/s10836-016-5619-8
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- Publication type:
- Article
Test Data Compression for System-on-chip using Flexible Runs-aware PRL Coding.
- Published in:
- Journal of Electronic Testing, 2016, v. 32, n. 5, p. 639, doi. 10.1007/s10836-016-5595-z
- By:
- Publication type:
- Article