Works matching DE "ADDERS (Digital electronics)"
Results: 81
Novel, low-supply, differential XOR/XNOR with rail-to-rail swing, for hamming-code generation.
- Published in:
- International Journal of Electronics Letters, 2018, v. 6, n. 3, p. 272, doi. 10.1080/21681724.2017.1357761
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- Article
SPEED COMPARISON OF THE ADDERS IN FPGA.
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- Science & Military Journal, 2013, v. 8, n. 1, p. 18
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- Article
Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder.
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- Computer Systems Science & Engineering, 2023, v. 46, n. 1, p. 2659, doi. 10.32604/csse.2023.025075
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- Article
Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder.
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- Computer Systems Science & Engineering, 2023, v. 45, n. 3, p. 2659, doi. 10.32604/csse.2023.025075
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- Article
DESIGN OF LOW POWER 14T FULL ADDER CELL USING DOUBLE GATE MOSFET WITH MTCMOS REDUCTION TECHNIQUE AT 45 NANOMETER TECHNOLOGY.
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- International Journal of Nanoscience, 2013, v. 12, n. 6, p. -1, doi. 10.1142/S0219581X13500427
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- Article
Design of novel efficient adder and subtractor for quantum-dot cellular automata.
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- International Journal of Circuit Theory & Applications, 2015, v. 43, n. 10, p. 1446, doi. 10.1002/cta.2019
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- Article
A framework for high-speed parallel-prefix adder performance evaluation and comparison.
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- International Journal of Circuit Theory & Applications, 2015, v. 43, n. 10, p. 1474, doi. 10.1002/cta.2020
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- Article
Simplified carry save adder-based array multiplier scheme and circuits design.
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- International Journal of Circuit Theory & Applications, 2015, v. 43, n. 9, p. 1226, doi. 10.1002/cta.1998
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- Article
Design of high-speed low-power parallel-prefix adder trees in nanometer technologies.
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- International Journal of Circuit Theory & Applications, 2014, v. 42, n. 7, p. 731, doi. 10.1002/cta.1886
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- Article
4-bit Brent Kung Parallel Prefix Adder Simulation Study Using Silvaco EDA Tools.
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- International Journal of Simulation: Systems, Science & Technology, 2012, v. 13, n. 3A, p. 51
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- Article
DLPA: Discrepant Low PDP 8-Bit Adder.
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- Circuits, Systems & Signal Processing, 2013, v. 32, n. 1, p. 1, doi. 10.1007/s00034-012-9438-6
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- Article
Unified architecture for 2, 3, 4, 5, and 7-point DFTs based on Winograd Fourier transform algorithm.
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- Electronics Letters (Wiley-Blackwell), 2013, v. 49, n. 5, p. 1, doi. 10.1049/el.2012.0577
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- Article
Principle and design of ternary optical accumulator implementing M-k-B addition.
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- Optical Engineering, 2014, v. 53, n. 9, p. 1, doi. 10.1117/1.OE.53.9.095108
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- Article
Turbo coding for the noisy 2-user binary adder channel with punctured convolutional codes.
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- Telecommunication Systems, 2017, v. 64, n. 3, p. 459, doi. 10.1007/s11235-016-0185-z
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- Article
Implementing a one-bit reversible full adder using quantum-dot cellular automata.
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- Quantum Information Processing, 2014, v. 13, n. 9, p. 2127, doi. 10.1007/s11128-014-0782-2
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- Article
Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints.
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- Journal of Electronic Testing, 2018, v. 34, n. 1, p. 7, doi. 10.1007/s10836-017-5701-x
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- Article
A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures.
- Published in:
- VLSI Design, 2013, p. 1, doi. 10.1155/2013/785281
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- Article
Faster and Energy-Efficient Signed Multipliers.
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- VLSI Design, 2013, p. 1, doi. 10.1155/2013/495354
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- Article
FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders.
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- VLSI Design, 2013, p. 1, doi. 10.1155/2013/382682
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- Article
Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL.
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- VLSI Design, 2013, p. 1, doi. 10.1155/2013/157872
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- Article
Redundant Logic Insertion and Latency Reduction in Self-Timed Adders.
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- VLSI Design, 2012, p. 1, doi. 10.1155/2012/575389
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- Article
Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic.
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- Electronics (2079-9292), 2018, v. 7, n. 10, p. 243, doi. 10.3390/electronics7100243
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- Article
Efficient Fused MAC Unit Using Multi-Operand Parallel Prefix Adder.
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- Radioelectronics & Communications Systems, 2022, v. 65, n. 4, p. 213, doi. 10.3103/S0735272722040057
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- Article
Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2016, v. 6, n. 3, p. 1205, doi. 10.11591/ijece.v6i3.9457
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- Article
A Novel Design of an Ultra Low Voltage Energy-Efficient Full Adder.
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- IUP Journal of Telecommunications, 2014, v. 6, n. 3, p. 53
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- Article
Optimally Factored IFIR Filters.
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- Circuits, Systems & Signal Processing, 2019, v. 38, n. 1, p. 259, doi. 10.1007/s00034-018-0857-x
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- Article
Area-Efficient Dual-Mode Fused Floating-Point Three-Term Adder.
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- Circuits, Systems & Signal Processing, 2019, v. 38, n. 1, p. 173, doi. 10.1007/s00034-018-0848-y
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- Article
Performance of CSE Techniques for Designing Multiplier-Less FIR Filter Using Evolutionary Algorithms.
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- Circuits, Systems & Signal Processing, 2018, v. 37, n. 6, p. 2574, doi. 10.1007/s00034-017-0679-2
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- Article
A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology.
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- Circuits, Systems & Signal Processing, 2015, v. 34, n. 3, p. 739, doi. 10.1007/s00034-014-9887-1
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- Article
Erratum to: A Symmetric, Multi-Threshold, High-Speed and Efficient-Energy 1-Bit Full Adder Cell Design Using CNFET Technology.
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- 2015
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- Erratum
A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures.
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- Circuits, Systems & Signal Processing, 2014, v. 33, n. 6, p. 1689, doi. 10.1007/s00034-013-9727-8
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- Article
Designing Dynamic Carry Skip Adders: Analysis and Comparison.
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- Circuits, Systems & Signal Processing, 2014, v. 33, n. 4, p. 1019, doi. 10.1007/s00034-013-9688-y
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- Article
A Novel CNTFET-based Ternary Full Adder.
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- Circuits, Systems & Signal Processing, 2014, v. 33, n. 3, p. 665, doi. 10.1007/s00034-013-9672-6
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- Article
Fully pipelined CORDIC-based inverse kinematic FPGA design for biped robots.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2015, v. 51, n. 16, p. 1241, doi. 10.1049/el.2015.1604
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- Article
Area efficient floating-point FFT butterfly architectures based on multi-operand adders.
- Published in:
- Electronics Letters (Wiley-Blackwell), 2015, v. 51, n. 12, p. 895, doi. 10.1049/el.2015.0342
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- Article
Design And Analysis Of 1-Bit Full Adder Using Cntfets.
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- Journal of VLSI Circuits & Systems (JVCS), 2020, v. 2, n. 1, p. 14, doi. 10.31838/jvcs/02.01.04
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- Article
Energy Efficient and Low Power Rca Based Full Adder.
- Published in:
- Journal of VLSI Circuits & Systems (JVCS), 2020, v. 2, n. 1, p. 6, doi. 10.31838/jvcs/02.01.02
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- Article
Formal Analysis of Hybrid Prefix/Carry-Select Arithmetic Systems.
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- Computer Journal, 2011, v. 54, n. 6, p. 894, doi. 10.1093/comjnl/bxq048
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- Article
A Fault Tolerant Adder Based On Alternative Computation.
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- International Journal of Design, Analysis & Tools for Integrated Circuits & Systems, 2012, v. 3, n. 1, p. 14
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- Article
Alternative Approach of Developing Optical Binary Adder Using Reversible Peres Gates.
- Published in:
- International Journal of Optics, 2018, p. 1, doi. 10.1155/2018/8541371
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- Article
Fast arithmetic in algorithmic self-assembly.
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- Natural Computing, 2016, v. 15, n. 1, p. 115, doi. 10.1007/s11047-015-9512-7
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- Article
Adaptive estimation of variable weights in a linear adder.
- Published in:
- Automation & Remote Control, 2013, v. 74, n. 4, p. 660, doi. 10.1134/S0005117913040085
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- Article
An optimized embedded adder for digital signal processing applications.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2016, v. 24, n. 6, p. 5224, doi. 10.3906/elk-1412-140
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- Article
Two Novel Quantum-Dot Cellular Automata Full Adders.
- Published in:
- Journal of Engineering (2314-4912), 2013, p. 1, doi. 10.1155/2013/561651
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- Publication type:
- Article
IMPROVED FLOATING POINT MULTIPLIER DESIGN BASED ON CANONICAL SIGN DIGIT.
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- International Journal of Technology, 2014, v. 5, n. 1, p. 22, doi. 10.14716/ijtech.v5i1.150
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- Publication type:
- Article
High Performance DIF-FFT Using Dissimilar Partitioned LUT Based Distributed Arithmetic.
- Published in:
- International Journal of Electronics & Telecommunications, 2021, v. 67, n. 4, p. 631, doi. 10.24425/ijet.2021.137856
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- Publication type:
- Article
Low Power and Area Efficient 2C Multiply-Accumulate Unit and Its Application to a DTMAC Unit.
- Published in:
- International Journal of Advanced Research in Computer Science, 2012, v. 3, n. 6, p. 45
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- Article
DEDICATED HARDWARE FOR COMPLEX MATHEMATICAL OPERATIONS.
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- Computing & Informatics, 2016, v. 35, n. 6, p. 1438
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- Article
Limited Carry-Propagate Multiply-Accumulate Unit Design for Reconfigurable Systems.
- Published in:
- Electronics & Electrical Engineering, 2017, v. 23, n. 2, p. 36, doi. 10.5755/j01.eie.23.2.17997
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- Article
Binary Implementation of Parallel Ternary Full Adder and Subtractor.
- Published in:
- International Review on Computers & Software, 2012, v. 7, n. 2, p. 495
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- Article