Works matching DE "CMOS logic circuits"
Results: 52
N-Type Conjugated Polymer-Enabled Selective Dispersion of Semiconducting Carbon Nanotubes for Flexible CMOS-Like Circuits.
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- Advanced Functional Materials, 2015, v. 25, n. 12, p. 1837, doi. 10.1002/adfm.201404126
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- Article
NVRH-LUT: A nonvolatile radiation-hardened hybrid MTJ/CMOS-based look-up table for ultralow power and highly reliable FPGA designs.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2019, v. 27, n. 6, p. 4486, doi. 10.3906/elk-1812-179
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- Article
A new CMOS logarithmic current generator.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2016, v. 24, n. 5, p. 4517, doi. 10.3906/elk-1503-146
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- Article
Clock Delayed Dual Keeper Semi Dynamic Inverter Domino Logic Circuit.
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- Journal of Active & Passive Electronic Devices, 2020, v. 15, n. 1/2, p. 53
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- Article
Performance Comparison of the Conventional CMOS and MTCMOS Digital Circuits and Their Simulation.
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- International Review of Electrical Engineering, 2022, v. 17, n. 1, p. 66, doi. 10.15866/iree.v17i1.20555
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- Article
An ultra-lightweight design for imperceptible plastic electronics.
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- Nature, 2013, v. 499, n. 7459, p. 458, doi. 10.1038/nature12314
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- Article
Low-Cost Synthesis Approach for Reversible Authenticator Circuits in QCA Environment.
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- International Journal of Nanoelectronics & Materials, 2019, v. 12, n. 2, p. 205
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- Article
Noise measurement in high-speed domino pseudo-CMOS keeper.
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- Measurement & Control (0020-2940), 2019, v. 52, n. 1/2, p. 20, doi. 10.1177/0020294018813642
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- Article
ANFIS Based Thermal Estimation of Ultradeep Submicron Digital Circuit Design.
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- Journal of Integrated Circuits & Systems, 2021, v. 16, n. 3, p. 1, doi. 10.29292/jics.v16i3.507
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- Article
Modeling of Temperature-Dependent Noise in Silicon Nanowire FETs including Self-Heating Effects.
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- Modelling & Simulation in Engineering, 2014, p. 1, doi. 10.1155/2014/635803
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- Article
Design of Memristor-Based Combinational Logic Circuits.
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- Circuits, Systems & Signal Processing, 2021, v. 40, n. 12, p. 5825, doi. 10.1007/s00034-021-01770-1
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- Article
Theory of Expansion Boolean Algebra and Its Applications in CMOS VLSI Digital Systems.
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- Circuits, Systems & Signal Processing, 2019, v. 38, n. 12, p. 5817, doi. 10.1007/s00034-019-01163-5
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- Article
1 V Rectifier Based on Bulk-Driven Quasi-Floating-Gate Differential Difference Amplifiers.
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- Circuits, Systems & Signal Processing, 2015, v. 34, n. 7, p. 2077, doi. 10.1007/s00034-014-9958-3
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- Article
CMOS X‐band pole‐converging triple‐cascode LNA with low‐noise and wideband performance.
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- IET Circuits, Devices & Systems (Wiley-Blackwell), 2022, v. 16, n. 1, p. 26, doi. 10.1049/cds2.12081
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- Article
An efficient 70 GHz divide‐by‐4 CMOS frequency divider employing low threshold devices.
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- Electronics Letters (Wiley-Blackwell), 2021, v. 57, n. 14, p. 545, doi. 10.1049/ell2.12171
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- Article
High-performance and single event double-upset-immune latch design.
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- Electronics Letters (Wiley-Blackwell), 2020, v. 56, n. 23, p. 1243, doi. 10.1049/el.2020.1823
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- Article
Error-compensated time integrator in 28-nm CMOS technology.
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- Electronics Letters (Wiley-Blackwell), 2020, v. 56, n. 16, p. 806, doi. 10.1049/el.2020.1074
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- Article
Challenges for Nanoscale CMOS Logic Based on Two-Dimensional Materials.
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- Nanomaterials (2079-4991), 2022, v. 12, n. 20, p. 3548, doi. 10.3390/nano12203548
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- Article
Design and Implementation of Low Power Multiplier Using Proposed Two Phase Clocked Adiabatic Static CMOS Logic Circuit.
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- International Journal of Electrical & Computer Engineering (2088-8708), 2018, v. 8, n. 6, p. 4959, doi. 10.11591/ijece.v8i6.pp4959-4971
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- Article
A 1‐Gbps reference‐less burst‐mode CDR with embedded TDC in a 65‐nm CMOS process.
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- International Journal of Circuit Theory & Applications, 2018, v. 46, n. 8, p. 1565, doi. 10.1002/cta.2490
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- Article
Low‐power, latch‐based multistage time‐to‐digital converter in 65 nm CMOS technology.
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- International Journal of Circuit Theory & Applications, 2018, v. 46, n. 6, p. 1264, doi. 10.1002/cta.2468
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- Article
Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS.
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- International Journal of Circuit Theory & Applications, 2018, v. 46, n. 6, p. 1129, doi. 10.1002/cta.2465
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- Article
Balanced G<sub>m</sub>-C filters with improved linearity and power efficiency.
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- International Journal of Circuit Theory & Applications, 2015, v. 43, n. 9, p. 1147, doi. 10.1002/cta.2001
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- Article
NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors.
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- Scientific Reports, 2022, v. 12, n. 1, p. 1, doi. 10.1038/s41598-022-07368-0
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- Article
266-2133 MHz phase shifter using all-digital delay-locked loop and triangular-modulated phase interpolator for LPDDR4X interface.
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- Electronics Letters (Wiley-Blackwell), 2017, v. 53, n. 12, p. 766, doi. 10.1049/el.2017.1291
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- Article
Optimal pipeline stage balancing in the presence of large isolated interconnect delay.
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- Electronics Letters (Wiley-Blackwell), 2017, v. 53, n. 4, p. 229, doi. 10.1049/el.2016.4262
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- Article
Nano-power tunable bump circuit using wide-input-range pseudo-differential transconductor.
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- Electronics Letters (Wiley-Blackwell), 2014, v. 50, n. 13, p. 921, doi. 10.1049/el.2014.0920
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- Article
Distributed range-free localisation algorithm for wireless sensor networks.
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- Electronics Letters (Wiley-Blackwell), 2014, v. 50, n. 12, p. 894, doi. 10.1049/el.2014.0787
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- Article
Compact inductorless CMOS low-noise amplifier for reconfigurable radio.
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- Electronics Letters (Wiley-Blackwell), 2014, v. 50, n. 12, p. 892, doi. 10.1049/el.2014.1031
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- Article
Design Analysis of AND (2T) and OR (2T) Based Low Power Full Adder Circuit.
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- International Journal of Advanced Research in Computer Science, 2014, v. 5, n. 4, p. 111
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- Article
Demonstration of PdSe<sub>2</sub> CMOS Using Same Metal Contact in PdSe<sub>2</sub> n‐/p‐MOSFETs through Thickness‐Dependent Phase Transition.
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- Advanced Electronic Materials, 2022, v. 8, n. 11, p. 1, doi. 10.1002/aelm.202200485
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- Article
CMOS Readout Circuit Integrated with Ionizing Radiation Detectors.
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- International Journal of Electronics & Telecommunications, 2014, v. 60, n. 1, p. 105, doi. 10.2478/eletel-2014-0014
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- Article
Spin-Based Fully Nonvolatile Full-Adder Circuit for Computing in Memory.
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- SPIN (2010-3247), 2019, v. 9, n. 1, p. N.PAG, doi. 10.1142/S2010324719500073
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- Article
The Window Comparator Circuit with CMOS and TTL Logic ICs Switching levels.
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- Przegląd Elektrotechniczny, 2024, v. 2024, n. 1, p. 112, doi. 10.15199/48.2024.01.23
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- Article
Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology.
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- Electronics (2079-9292), 2024, v. 13, n. 15, p. 2993, doi. 10.3390/electronics13152993
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- Article
Design and Validation of a V-Gate n-MOSFET-Based RH CMOS Logic Circuit with Tolerance to the TID Effect.
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- Electronics (2079-9292), 2023, v. 12, n. 15, p. 3331, doi. 10.3390/electronics12153331
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- Article
Delay Insensitive Ternary CMOS Logic for Secure Hardware.
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- Journal of Low Power Electronics & Applications, 2015, v. 5, n. 3, p. 183, doi. 10.3390/jlpea5030183
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- Article
Multi-Threshold NULL Convention Logic (MTNCL): An Ultra-Low Power Asynchronous Circuit Design Methodology.
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- Journal of Low Power Electronics & Applications, 2015, v. 5, n. 2, p. 81, doi. 10.3390/jlpea5020081
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- Article
A Robust Ultra-Low Voltage CPU Utilizing Timing-Error Prevention.
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- Journal of Low Power Electronics & Applications, 2015, v. 5, n. 2, p. 57, doi. 10.3390/jlpea5020057
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- Article
Circuit Level Implementation for Insulated Shallow Extension Silicon on Nothing (ISE-SON) MOSFET: A Novel Device Architecture.
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- IETE Journal of Research, 2013, v. 59, n. 4, p. 404, doi. 10.4103/0377-2063.118053
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- Article
Automatic Crack Detection and Classification Method for Subway Tunnel Safety Monitoring.
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- Sensors (14248220), 2014, v. 14, n. 10, p. 19307, doi. 10.3390/s141019307
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- Article
A Linearity-Enhanced Time-Domain CMOS Thermostat with Process-Variation Calibration.
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- Sensors (14248220), 2014, v. 14, n. 10, p. 18784, doi. 10.3390/s141018784
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- Article
Power saving bidirectional optical transceiver design and fabrication.
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- Optical & Quantum Electronics, 2015, v. 47, n. 8, p. 3101, doi. 10.1007/s11082-015-0198-y
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- Article
Accurate Calculation of Unreliability of CMOS Logic Cells and Circuits.
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- Journal of Circuits, Systems & Computers, 2020, v. 29, n. 13, p. N.PAG, doi. 10.1142/S0218126620502023
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- Article
Comparative Study Between Two Novel BJT-DVCC and CMOS-DVCC.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500748
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- Article
60 GHz-Band Low-Noise Amplifier.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S021812661750075X
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- Article
A CMOS LNA Partially Degenerated Topology Proposal Using Active Inductors.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500785
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- Article
Design and Optimization of Differential Ring Oscillator for IR-UWB Applications in 0.18 m CMOS Technology.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500803
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- Article
An Energy Efficient Logic Approach to Implement CMOS Full Adder.
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- Journal of Circuits, Systems & Computers, 2017, v. 26, n. 5, p. -1, doi. 10.1142/S0218126617500840
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- Article
On the role of astrocyte analog circuit in neural frequency adaptation.
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- Neural Computing & Applications, 2017, v. 28, n. 5, p. 1109, doi. 10.1007/s00521-015-2112-8
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- Article