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- Title
A Low-Complexity Edward-Curve Point Multiplication Architecture.
- Authors
Sajid, Asher; Rashid, Muhammad; Imran, Malik; Jafri, Atif Raza
- Abstract
The Binary Edwards Curves (BEC) are becoming more and more important, as compared to other forms of elliptic curves, thanks to their faster operations and resistance against side channel attacks. This work provides a low-complexity architecture for point multiplication computations using BEC over G F (2 233) . There are three major contributions in this article. The first contribution is the reduction of instruction-level complexity for unified point addition and point doubling laws by eliminating multiple operations in a single instruction format. The second contribution is the optimization of hardware resources by minimizing the number of required storage elements. Finally, the third contribution is to reduce the number of required clock cycles by incorporating a 32- b i t finite field digit-parallel multiplier in the datapath. As a result, the achieved throughput over area ratio over G F (2 233) on Virtex-4, Virtex-5, Virtex-6 and Virtex-7 Xilinx FPGA (Field Programmable Gate Array) devices are 2.29, 19.49, 21.5 and 20.82, respectively. Furthermore, on the Virtex-7 device, the required computation time for one point multiplication operation is 18 µs, while the power consumption is 266 mW. This reveals that the proposed architecture is best suited for those applications where the optimization of both area and throughput parameters are required at the same time.
- Subjects
FIELD programmable gate arrays; MULTIPLICATION; FINITE fields
- Publication
Electronics (2079-9292), 2021, Vol 10, Issue 9, p1080
- ISSN
2079-9292
- Publication type
Article
- DOI
10.3390/electronics10091080