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- Title
Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator.
- Authors
Shehzad, Khuram; Verma, Deeksha; Khan, Danial; Ain, Qurat Ul; Basim, Muhammad; Kim, Sung Jin; Pu, YoungGun; Hwang, Keum Cheol; Yang, Youngoo; Lee, Kang-Yoon
- Abstract
This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CVREF2 switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic part, a modified asynchronous type SAR control logic with digitally controllable delay cells is adopted. An on-chip reference voltage generator is also designed with an ADC core for practical use. The structure is realized using 55-nm complementary metal–oxide–semiconductor (CMOS) process technology. The proposed architecture achieves an effective number of bits (ENOB) of 9.56 bits and a signal-to-noise and distortion ratio (SNDR) level of 59.3 dB with a sampling rate of 8 MS/s at measurement level. The whole architecture consumes only 572 µW power when a power supply of 1 V is applied.
- Subjects
SUCCESSIVE approximation analog-to-digital converters; VOLTAGE references; DIGITAL-to-analog converters; ADAPTIVE control systems; SIGNAL-to-noise ratio; POWER resources
- Publication
Electronics (2079-9292), 2020, Vol 9, Issue 5, p872
- ISSN
2079-9292
- Publication type
Article
- DOI
10.3390/electronics9050872