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- Title
Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets.
- Authors
Chen, Kun; Yang, Jingwen; Liu, Tao; Wang, Dawei; Xu, Min; Wu, Chunlei; Wang, Chen; Xu, Saisheng; Zhang, David Wei; Liu, Wenchao
- Abstract
A new S/D trimming process was proposed to significantly reduce the parasitic RC of gate-all-around (GAA) nanosheet transistors (NS-FETs) while retaining the channel stress from epitaxy S/D stressors at most. With optimized S/D trimming, the 7-stage ring oscillator (RO) gained up to 27.8% improvement of delay with the same power consumption, for a 3-layer stacked GAA NS-FETs. Furthermore, the proposed S/D trimming technology could enable more than 4-layer vertical stacking of nanosheets for GAA technology extension beyond 3 nm CMOS technology.
- Subjects
NANOSTRUCTURED materials; TRANSISTORS; METAL semiconductor field-effect transistors; EPITAXY
- Publication
Micromachines, 2022, Vol 13, Issue 7, pN.PAG
- ISSN
2072-666X
- Publication type
Article
- DOI
10.3390/mi13071080