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- Title
A Novel Least Significant Bit First Processing Parallel CRC Circuit.
- Authors
Xiujie Qu; Zhongkai Cao; Zhanjie Yang
- Abstract
In HDLC serial communication protocol, CRC calculation can first process the most or least significant bit of data. Nowadays most CRC calculation is based on the most significant bit (MSB) first processing. An algorithm of the least significant bit (LSB) first processing parallel CRC is proposed in this paper. Based on the general expression of the least significant bit first processing serial CRC, using state equation method of linear system, we derive a recursive formula by the mathematical deduction. The recursive formula is applicable to any number of bits processed in parallel and any series of generator polynomial. According to the formula, we present the parallel circuit of CRC calculation and implement it with VHDL on FPGA. The results verify the accuracy and effectiveness of this method.
- Subjects
SERIAL communications; BIT rate; ELECTRIC circuits; RECURSIVE functions; LINEAR systems; POLYNOMIALS
- Publication
Advances in Mechanical Engineering (Sage Publications Inc.), 2013, Vol 5, p1
- ISSN
1687-8132
- Publication type
Article
- DOI
10.1155/2013/859317