We found a match
Your institution may have rights to this item. Sign in to continue.
- Title
A CONFIGURABLE BOSE-CHAUDHURI-HOCQUENGHEM CODEC ARCHITECTURE FOR FLASH CONTROLLER APPLICATIONS.
- Authors
FREUDENBERGER, JÜRGEN; SPINNER, JENS
- Abstract
Error correction coding (ECC) has become one of the most important tasks of flash memory controllers. The gate count of the ECC unit is taking up a significant share of the overall logic. Scaling the ECC strength to the growing error correction requirements has become increasingly difficult when considering cost and area limitations. This work presents a configurable encoding and decoding architecture for binary Bose-Chaudhuri-Hocquenghem (BCH) codes. The proposed concept supports a wide range of code rates and facilitates a trade-off between throughput and space complexity. Commonly, hardware implementations for BCH decoding perform many Galois field multiplications in parallel. We propose a new decoding technique that uses different parallelization degrees depending on the actual number of errors. This approach significantly reduces the number of required multipliers, where the average number of decoding cycles is even smaller than with a fully parallel implementation.
- Subjects
CODECS; COMPUTER architecture; ERROR correction (Information theory); FLASH memory; PARALLEL computers
- Publication
Journal of Circuits, Systems & Computers, 2014, Vol 23, Issue 2, p-1
- ISSN
0218-1266
- Publication type
Article
- DOI
10.1142/S0218126614500194