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- Title
700 V ultra-low on-resistance DB-nLDMOS with optimised thermal budget and neck region.
- Authors
Kun Mao; Ming Qiao; Zhaoji Li; Bo Zhang
- Abstract
An ultra-low Ron,sp 700 V DB-nLDMOS (dual P-buried-layer nLDMOS) which uses 0.35 μm technology and full ion implantation technology is proposed. Experimental results show that with 800 V BVds, Ron,sp is only 10.7 Ω·mm2 which is the lowest value of triple RESURF (REduce SURface Field) LDMOS reported before. This mainly benefits from two aspects. First, thermal budgets of the process are strictly limited after implantation of the Pbury layer. Secondly, device sizes of the neck region are optimised to reduce Ron,sp which also suppress the JFET effect of the triple RESURF LDMOS.
- Subjects
ION plating; ION bombardment; ION implantation; SEMICONDUCTORS; ELECTRIC conductivity
- Publication
Electronics Letters (Wiley-Blackwell), 2014, Vol 50, Issue 3, p1
- ISSN
0013-5194
- Publication type
Article
- DOI
10.1049/el.2013.2287