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- Title
New High-Rate Timestamp Management with Real-Time Configurable Virtual Delay and Dead Time for FPGA-Based Time-to-Digital Converters.
- Authors
Garzetti, Fabio; Bonanno, Gabriele; Lusardi, Nicola; Ronconi, Enrico; Costa, Andrea; Geraci, Angelo
- Abstract
Modern applications require the ability to measure time events with high resolution, a full-scale range, and multiple input channels. Time-to-Digital Converters (TDCs) are a popular option to convert time intervals into timestamps. To reduce the time-to-market and Non-Recurring Engineering (NRE) costs, a Field-Programmable Gate Array (FPGA) implementation has been chosen. The high number of requested bits and channels, however, gives rise to routing congestion issues when routed in a parallel manner. In this paper, we will propose and analyze a novel solution, the Belt-Bus (BB), which involves a parallel-to-serial conversion of the timestamp stream coming from the TDC while maintaining chronological order and a sufficient high rate, and flagging the presence of timestamp overflow. Moreover, two new useful features are added. The first is a "Virtual Delay" to compensate for offsets due to cable length and FPGA routing path mismatch. The second is a "Virtual Dead-Time" to filter out unforeseen events. Finally, the BB was tested on a Xilinx 28 nm 7-Series Kintex-7 325T FPGA, achieving an overall data rate of 199.9 Msps with very limited resource usage (i.e., lower than a total of 4.5%), consuming only 480 mW in a 16-channel implementation.
- Subjects
TIME-digital conversion; GATE array circuits; FIELD programmable gate arrays; TIMESTAMPS
- Publication
Electronics (2079-9292), 2024, Vol 13, Issue 6, p1124
- ISSN
2079-9292
- Publication type
Article
- DOI
10.3390/electronics13061124