We found a match
Your institution may have rights to this item. Sign in to continue.
- Title
Optimized test ports selecting method on 3D-NoC.
- Authors
XU Chuan-pei; YAO Yong-xing
- Abstract
This paper proposed a method to select and optimize test ports for shortening test time, under the test power consumption constraints. It selected the appropriate number of the test ports according to the system power consumption constraints ' optimized location of the test ports for core to make the core test resources and test time minimum. Cloud based evolution algorithm" CBEA) optimized diiferent test ports combinations, strong convergence of CBEA enabled CBEA to be able to find accurate test ports within a short time, completed test method research. Experiments with ITC02 test circuits as the simulation object'experimental results of diiferent scales NoC show that this way can improve the eeficiency of test, shorten test time, and decrease the test cost.
- Publication
Application Research of Computers / Jisuanji Yingyong Yanjiu, 2015, Vol 32, Issue 3, p810
- ISSN
1001-3695
- Publication type
Article
- DOI
10.3969/j.issn.1001-3695.2015.03.038