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- Title
PAGE—Practical AES-GCM Encryption for Low-End Microcontrollers.
- Authors
Kim, Kyungho; Choi, Seungju; Kwon, Hyeokdong; Kim, Hyunjun; Liu, Zhe; Seo, Hwajeong
- Abstract
An optimized AES (Advanced Encryption Standard) implementation of Galois Counter Mode of operation (GCM) on low-end microcontrollers is presented in this paper. Two optimization methods are applied to proposed implementations. First, the AES counter (CTR) mode of operation is speed-optimized and ensures constant timing. The main idea is replacing expensive AES operations, including AddRound Key, SubBytes, ShiftRows, and MixColumns, into simple look-up table access. Unlike previous works, the look-up table does not require look-up table updates during the entire encryption life-cycle. Second, the core operation of Galois Counter Mode (GCM) is optimized further by using Karatsuba algorithm, compact register utilization, and pre-computed operands. With above optimization techniques, proposed AES-GCM on 8-bit AVR (Alf and Vegard's RISC processor) architecture from short-term, middle-term to long-term security levels achieved 415, 466, and 477 clock cycles per byte, respectively.
- Subjects
ADVANCED Encryption Standard; MICROCONTROLLERS; MATHEMATICAL optimization; REDUCED instruction set computers
- Publication
Applied Sciences (2076-3417), 2020, Vol 10, Issue 9, p3131
- ISSN
2076-3417
- Publication type
Article
- DOI
10.3390/app10093131