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- Title
Design of IP core for IIC bus controller based on FPGA.
- Authors
HUANG Xiao-min; ZHANG Zhi-jie
- Abstract
The intellectual property (IP) core for inter-integrated circuit (IIC) bus controller is designed using finite state machine (FSM) based on field programmable gate array (FPGA). Not only the data from AT24C02C can he read automatically after power on. but also the data from upper computer can he written into AT24C02C immediately under the control of the IIC bus controller. When it Is applied to blast wave overpressure test system, the IIC bus controller can read and store working parameters automatically. In a laboratory environment, the IP core simulation is carried out and the result is accurate. In the explosion field test, by analyzing the obtained valid data, it can be concluded that the designed IP core has good reliability.
- Subjects
I2C (Computer bus); FIELD programmable gate arrays -- Design &; construction; FINITE state machines; DATA management; INFORMATION storage &; retrieval systems; COMPUTER software
- Publication
Journal of Measurement Science & Instrumentation, 2015, Vol 6, Issue 1, p13
- ISSN
1674-8042
- Publication type
Article
- DOI
10.3969/j.issn.1674-8042.2015.01.003