We found a match
Your institution may have rights to this item. Sign in to continue.
- Title
"LogN+1" and "LogN" model: a binary tree based multi-level cache system for multi-core processors.
- Authors
Ismail, Muhammad Ali; Mirza, Shahid H.; Altaf, Talat
- Abstract
In this paper a novel multi-level cache system design for multi-core processors Is presented. Its two possible implementations (models) LogN+1 and LogN are studied. Important cache performances matrices like average cache access time and hit / miss ratio at different cache levels are calculated. Firstly, these two proposed models are analyzed and compared with the present 3-level cache system using a probabilistic mathematical model. Secondly the same models are modelled and analyzed using M/D/C/K queuing network. For evaluating the proposed models in real time environment a parallel trace-driven multi-level cache simulator is also developed. On comparing the results based on two mathematical models and simulations, it is found that, for higher number of cores the proposed cache system work much better than the present 3-level cache system. The performance gain increases as the number of cores increases. Average cache access time of the proposed cache system found much improved than present 3-level cache system and the probability of finding the data at L1 and L2 in proposed cache system is also found to be much greater than present 3-level cache system.
- Subjects
TREE graphs; GRAPH theory; MULTILEVEL models; CACHE memory; MULTICORE processors; QUEUEING networks
- Publication
Computer Systems Science & Engineering, 2014, Vol 29, Issue 2, p131
- ISSN
0267-6192
- Publication type
Article