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- Title
Reconfigurable Turbo and Low-Density Parity-Check (LDPC) Decoding Accelerators for Powerline Communications.
- Authors
Lin, Cheng-Hung; Shen, Jin-Kun; Lu, Cheng-Kai
- Abstract
This study presents two reconfigurable turbo/low-density parity-check (LDPC) decoding kernels for the two powerline communication standards, HomePlug and G.hn. Two architectures are presented, both of which use the radix-4 double-binary enhanced max-log maximum a posteriori probability algorithm with next-iteration initialization in turbo decoding. In LDPC decoding, the two architectures employ the normalized min-sum and the layered radix-4 forward and backward algorithms. The two algorithms cause differences in the architecture and throughput rate. Consequently, the proposed decoding kernels have different architectures when combined with the turbo decoding algorithm, and the two proposed decoding kernels each have their own advantages and disadvantages in terms of throughput and area cost. To make the features of two kernels more evident, we have implemented the proposed decoding kernels that lead to significant throughput gains and better area efficiency compared with other studies. The proposed decoding kernels can be operated in all modes specified in the HomePlug and G.hn standards using a 40-nm complementary metal-oxide-semiconductor (CMOS) process. Moreover, the proposed decoding kernels provide different solutions to achieve the expected throughput rates of the G.hn and HomePlug standards.
- Subjects
DECODING algorithms; TURBO codes; LOW density parity check codes
- Publication
Journal of Circuits, Systems & Computers, 2022, Vol 31, Issue 18, p1
- ISSN
0218-1266
- Publication type
Article
- DOI
10.1142/S0218126622503091