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- Title
Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs.
- Authors
Barkalov, Alexander; Titarenko, Larysa; Chmielewski, Sławomir
- Abstract
A method is proposed targeting the decrease of the number of look-up tables (LUTs) in logic circuits of field programmable gate arrays (FPGA)-based Mealy finite state machines. The method is based on constructing a partition for the set of output variables. It diminishes the number of additional variables encoding the collections of output variables (COVs). A formal method is proposed for finding the partition. An example of synthesis is given, as well as the results of investigations. The investigations were conducted for standard benchmarks.
- Subjects
FIELD programmable gate arrays; FINITE state machines; LOGIC circuits
- Publication
Journal of Circuits, Systems & Computers, 2019, Vol 28, Issue 8, pN.PAG
- ISSN
0218-1266
- Publication type
Article
- DOI
10.1142/S0218126619501317