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- Title
Error Correction Schemes with Erasure Information for Fast Memories.
- Authors
Evain, Samuel; Savin, Valentin; Gherman, Valentin
- Abstract
Two error correction schemes are proposed for word-oriented binary memories that can be affected by erasures, i.e. errors with known location but unknown value. The erasures considered here are due to the drifting of the electrical parameter used to encode information outside the normal ranges associated to a logic 0 or a logic 1 value. For example, a dielectric breakdown in a magnetic memory cell may reduce its electrical resistance sensibly below the levels which correspond to logic 0 and logic 1 values stored in healthy memory cells. Such deviations can be sensed during memory read operations and the acquired information can be used to boost the correction capability of an error-correcting code (ECC). The proposed schemes enable the correction of double-bit errors based on the combination of erasure information with single-bit error correction and double-bit error detection (SEC-DED) codes or shortened (SEC) codes. The correction of single-bit errors is always guaranteed. Ways to increase the number of double-bit and triple-bit errors that can be detected by shortened SEC and SEC-DED codes are considered in order to augment the error correction capability of the proposed solutions.
- Subjects
DIELECTRICS research; ERROR correction (Information theory); ERROR-correcting codes; MAGNETIC memory (Computers); ELECTRIC resistance
- Publication
Journal of Electronic Testing, 2014, Vol 30, Issue 2, p183
- ISSN
0923-8174
- Publication type
Article
- DOI
10.1007/s10836-014-5440-1