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- Title
Efficient Hardware Implementation of Pseudo-Random Bit Generator Using Dual-CLCG Method.
- Authors
Gupta, Mangal Deep; Chauhan, R. K.
- Abstract
In this work, the architecture of a dual-coupled linear congruential generator (dual-CLCG) for pseudo-random bit generation is proposed to improve the speed of the generator and minimize power dissipation with the optimum chip area. To improve its performance, a new pseudo-random bit generator (PRBG) employing two-operand modulo adder and without shifting operation-based dual-CLCG architecture is proposed. The novelty of the proposed dual-CLCG architecture is the designing of LCG based on two-operand modulo adder rather than a three-operand one and without using shifting operation as compared to the existing LCG architecture. The aim of the work is to generate pseudo-random bits at a uniform clock rate at the maximum clock frequency and achieve maximum length of the random bit sequence. The power dissipation with the optimum chip area of PRBG is also observed for the proposed architecture. The generated sequence passes all the 15 tests of the National Institute of Standards and Technology (NIST) standard. Verilog HDL code is used for the design of the proposed architecture. Its simulation is done on commercially available Spartan-3E FPGA (ISE Design Suite by Xilinx) as well as on 90-nm CMOS technology (Cadence tool).
- Subjects
NATIONAL Institute of Standards &; Technology (U.S.); NATIONAL competency-based educational tests; ARCHITECTURAL design
- Publication
Journal of Circuits, Systems & Computers, 2021, Vol 30, Issue 10, p1
- ISSN
0218-1266
- Publication type
Article
- DOI
10.1142/S0218126621501826