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- Title
PAFSV: A FORMAL FRAMEWORK FOR SPECIFICATION AND ANALYSIS OF SYSTEMVERILOG.
- Authors
Ka Lok MAN; Chi-Un LEI; Kapoor, Hemangee K.; KRILAVIČIUS, Tomas; Jieming MA; Nan ZHANG
- Abstract
We develop a process algebraic framework PAFSV for the formal specification and analysis of IEEE 1800™ SystemVerilog designs. The formal semantics of PAFSV is defined by means of deduction rules that associate a time transition system with a PAFSV process. A set of properties of PAFSV is presented for a notion of bisimilarity. PAFSV may be regarded as the formal language of a significant subset of IEEE 1800™ System Verilog. To show that PAFSV is useful for the formal specification and analysis of IEEE 1800™ System Verilog designs, we illustrate the use of PAFSV with a multiplexer, a synchronous reset D flip-flop and an arbiter.
- Subjects
VERILOG (Computer hardware description language); COMPUTER hardware description languages; COMPUTER simulation of integrated circuits; ALGEBRA; MATHEMATICS
- Publication
Computing & Informatics, 2016, Vol 35, Issue 1, p143
- ISSN
1335-9150
- Publication type
Article