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- Title
터널링 전계효과 트랜지스터로 구성된 3차원 적층형 집적회로에 대한 연구.
- Authors
유윤섭
- Abstract
In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.
- Subjects
METAL oxide semiconductor field-effect transistors; FIELD-effect transistors; LOGIC circuits; TUNNEL field-effect transistors; COMPUTER-aided design; NAND gates
- Publication
Journal of the Korea Institute of Information & Communication Engineering, 2022, Vol 26, Issue 5, p682
- ISSN
2234-4772
- Publication type
Article
- DOI
10.6109/jkiice.2022.26.5.682