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- Title
A-DSCNN: Depthwise Separable Convolutional Neural Network Inference Chip Design Using an Approximate Multiplier.
- Authors
Shang, Jin-Jia; Phipps, Nicholas; Wey, I-Chyn; Teo, Tee Hui
- Abstract
For Convolutional Neural Networks (CNNs), Depthwise Separable CNN (DSCNN) is the preferred architecture for Application Specific Integrated Circuit (ASIC) implementation on edge devices. It benefits from a multi-mode approximate multiplier proposed in this work. The proposed approximate multiplier uses two 4-bit multiplication operations to implement a 12-bit multiplication operation by reusing the same multiplier array. With this approximate multiplier, sequential multiplication operations are pipelined in a modified DSCNN to fully utilize the Processing Element (PE) array in the convolutional layer. Two versions of Approximate-DSCNN (A-DSCNN) accelerators were implemented on TSMC 40 nm CMOS process with a supply voltage of 0.9 V. At a clock frequency of 200 MHz, the designs achieve 4.78 GOPs/mW and 4.89 GOP/mW power efficiency while occupying 1.16 mm 2 and 0.398 mm 2 area, respectively.
- Subjects
CONVOLUTIONAL neural networks; INTEGRATED circuits; VOLTAGE; ANALOG multipliers; ARCHITECTURE
- Publication
Chips, 2023, Vol 2, Issue 3, p159
- ISSN
2674-0729
- Publication type
Article
- DOI
10.3390/chips2030010