We found a match
Your institution may have access to this item. Find your institution then sign in to continue.
- Title
New Configuration of a PLDRO with an Interconnected Dual PLL Structure for K-Band Application.
- Authors
Yuseok Jeon; Sungil Bang
- Abstract
A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.
- Subjects
DIELECTRIC resonator oscillators; DIGITAL phase locked loops; PHASE noise
- Publication
Journal of Electromagnetic Engineering & Science, 2017, Vol 17, Issue 3, p138
- ISSN
2671-7255
- Publication type
Article
- DOI
10.5515/JKIEES.2017.17.3.138