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- Title
28-nm CMOS 공정을 이용한 D-대역 저잡음 증폭기.
- Authors
김민우; 전상근
- Abstract
This paper presents a D-band low-noise amplifier using a 28-nm CMOS process. The low-noise amplifier consists of four differential common-source stages, each adopting a capacitance neutralization technique to improve stability and gain. Impedance matching is implemented using a transformer and a transmission line. To reduce the imbalance in the differential signal, a bypass capacitor was connected to the transformer, and the input and output transformers were optimized for impedance by connecting the capacitance to the single-ended signal path. The measurement shows that the low-noise amplifier exhibits a peak gain of 17.8 dB at 139 GHz and a 3-dB bandwidth of 20 GHz. The total chip area including the pads is 0.4 mm² and the dc power consumption is 50.2 mW.
- Subjects
IMPEDANCE matching; COMPLEMENTARY metal oxide semiconductors; ELECTRIC lines; ELECTRIC capacity; CAPACITORS; DIFFERENTIAL amplifiers; LOW noise amplifiers
- Publication
Journal of Korean Institute of Electromagnetic Engineering & Science / Han-Guk Jeonjapa Hakoe Nonmunji, 2023, Vol 34, Issue 3, p171
- ISSN
1226-3133
- Publication type
Article
- DOI
10.5515/KJKIEES.2023.34.3.171