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- Title
Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity.
- Authors
Crawford, O.; Cruise, J. R.; Mertig, N.; Gonzalez-Zalba, M. F.
- Abstract
Inspired by the challenge of scaling-up existing silicon quantum hardware, we propose a 2d spin-qubit architecture with low compilation overhead. The architecture is based on silicon nanowire split-gate transistors which form 1d chains of spin-qubits and allow the execution of two-qubit operations among neighbors. We introduce a silicon junction which can couple four nanowires into 2d arrangements via spin shuttling and Swap operations. We then propose a modular sparse 2d spin-qubit architecture with unit cells of diagonally-oriented squares with nanowires along the edges and junctions on the corners. Targeting noisy intermediate-scale quantum (NISQ) demonstrators, we show that the proposed architecture allows for compilation strategies which outperform methods for 1d chains, and exhibits favorable scaling properties which enable trading-off compilation overhead and colocation of control electronics within each square by adjusting the nanowire length. An appealing feature of the proposed architecture is its manufacturability using complementary-metal-oxide-semiconductor (CMOS) fabrication processes.
- Subjects
NANOWIRE devices; SILICON nanowires; SILICON; UNIT cell; NANOWIRES; BASES (Architecture)
- Publication
NPJ Quantum Information, 2023, Vol 9, Issue 1, p1
- ISSN
2056-6387
- Publication type
Article
- DOI
10.1038/s41534-023-00679-8