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- Title
Reducing the Length of the Test Sequence for Analog Test Signal Generation.
- Authors
Ting Long; Jiang Shiqi; Xu Lijia
- Abstract
In this paper we introduce a novel test signal generation method for the analog systems based on the SVM (support vector machine). Considering a circuit whose output signals cannot be classified with linear hyperplanes (i.e., the circuit has only small parametric faults), the responses of the normal instances are similar to those of the faulty instances, then the traditional test generation methods have difficulty generating the test signals. However, the SVM provides an effective result. Then we compress the test signals by measuring the Euclidean distance of different sample vectors obtained by the circuit instances in the feature space of SVM. It can reduce the length of the test sequence and save the cost of hardware and software in testing. A large number of experiments confirm that this method can ensure correct compression rates and precision of the test generation.
- Subjects
ANALOG electronic systems; SUPPORT vector machines; HYPERPLANES; DATA compression; AUTOMATIC test equipment
- Publication
Electrotechnical Review / Elektrotehniski Vestnik, 2015, Vol 82, Issue 1/2, p8
- ISSN
0013-5852
- Publication type
Article