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- Title
HLSMN: High Level Multicore NUMA Simulator.
- Authors
Slimane, Mohammed; Sekhri, Larbi
- Abstract
Multisocket multicore platforms have proven to be a trend in computing systems due to its scalability. It is designed to avoid shared bus constraint exposed by classical design of multicore processors, which is based on shared canal connecting processing units and shared storage unit. Such architecture with poor designed scheduling and mapping policies leads quickly to system performance degradation especially when it has complex design. Therefore, the problem of scheduling and data placement in this context becomes more challenging and urgent to solve. Testing the new and adapted policies or tuning parameters of a specified one for range of Non-Uniform Memory Access (NUMA) target platforms is costly, not practical in most cases. So, simulating the impact of these policies allows improving the system performance with low cost. In this paper, we present HLSMN, a simulation framework for multisocket-multicore NUMA systems based on HWLOC topology description in multithreaded fashion. The simulator supports core components of NUMA platform (node, interconnects and memory hierarchy). Its primary purpose is to allow to study the impact of combining different scheduling policies and data locality of parallel applications execution on the system overall performance testing them on several NUMA target platform topologies.
- Subjects
NON-uniform memory access; MULTICORE processors; SIMULTANEOUS multithreading processors
- Publication
Electrotehnica, Electronica, Automatica, 2017, Vol 65, Issue 3, p170
- ISSN
1582-5175
- Publication type
Article