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- Title
A 128 Gbps PAM‐4 feed forward equaliser with optimized 1UI pulse generator in 65 nm CMOS.
- Authors
Wang, Jiawei; Xu, Hao; Wang, Ziqiang; Jia, Haikun; Jiang, Hanjun; Zhang, Chun; Wang, Zhihua
- Abstract
Along with the bandwidth- and power-efficient partially segmented tailless 1-stage front-end architecture, the proposed FFE achieves 128 Gbps PAM-4 data rate with a 0.014 mm SP 2 sp area. Along with the bandwidth- and power-efficient partially segmented tailless 1-stage front-end architecture, the proposed FFE achieves 128Gbps PAM-4 data rate with a 0.014 mm SP 2 sp area. A quarter-rate PAM-4 FFE employing INCC 1UIPG is implemented in 65 nm CMOS. This letter presents a 4-level Pulse Amplitude Modulation (PAM-4) Feed Forward Equaliser (FFE) with a novel Internal Node Charge Controlled 1-Unit Interval Pulse Generator (INCC 1UIPG).
- Subjects
PULSE generators; DIGITAL-to-analog converters; PULSE amplitude modulation; CIRCUIT complexity
- Publication
IET Circuits, Devices & Systems (Wiley-Blackwell), 2023, Vol 17, Issue 3, p174
- ISSN
1751-858X
- Publication type
Article
- DOI
10.1049/cds2.12151