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- Title
Super-Threshold Adiabatic FinFET SRAM with PAL-2N Logic.
- Authors
Yuejie Zhang; Jianping Hu; Tianfang Ma; Beibei Qi
- Abstract
With IC process scaling, the leakage consumption has been an important factor in the power consumption of IC chips, which limits the scaling of SRAM. The FinFET device has the advantage in lower leakage current and higher on-state current than the CMOS devices. In this paper, a FinFET SRAM is verified by using adiabatic computing. All the circuits of the SRAM except for the storage array are realized by PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits. The storage uses 8T cell that can improve the read margin and keep the write current against the synchronous read/write disturb. All circuits are simulated with HSPICE at a PTM (Predictive Technology Model) 32nm FinFET technology. The results indicated that the energy consumption of the adiabatic FinFET SRAM decreased 49% compared with the SRAM based on CMOS devices.
- Subjects
STATIC random access memory chips; ADIABATIC quantum computation; ENERGY consumption
- Publication
Metallurgical & Mining Industry, 2015, Issue 9, p1134
- ISSN
2076-0507
- Publication type
Article