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- Title
Power bumps and through‐silicon‐vias placement with optimised power mesh structure for power delivery network in three‐dimensional‐integrated circuits.
- Authors
Jang, Cheoljon; Kim, Jaehwan; Ahn, Byunggyu; Chong, Jongwha
- Abstract
Three‐dimensional‐integrated circuits (3D‐ICs) bring new issues for power delivery network design because of larger current density and more complicated power delivery paths compared to 2D‐IC. The power delivery network consists of power bumps, through‐silicon‐vias (TSVs), and power wires. IR‐drop at each node varies with the number and position of power bumps and TSVs. These three power resources affect IR‐drop of 3D‐ICs. In this study, the authors propose power delivery network design methodology to optimise power resources wherease IR‐drop constraint is satisfied. The simulation results show that the proposed method minimises the number of power bumps and TSVs compared to the conventional method.
- Publication
IET Computers & Digital Techniques (Wiley-Blackwell), 2013, Vol 7, Issue 1, p11
- ISSN
1751-8601
- Publication type
Article
- DOI
10.1049/iet-cdt.2012.0047