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- Title
A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation.
- Authors
Ching-Lung Su; Tse-Min Chen; Kuo-Hsuan Wu
- Abstract
A prototype-based SoC performance estimation methodology was proposed for consumer electronics design. Traditionally, prototypes are usually used in system verification before SoC tapeout, which is without accurate SoC performance exploration and estimation. This paper attempted to carefully model the SoC prototype as a performance estimator and explore the environment of SoC performance. The prototype met the gate-level cycle-accurate requirement, which covered the effect of embedded processor, on-chip bus structure, IP design, embedded OS, GUI systems, and application programs. The prototype configuration, chip post-layout simulation result, and the measured parameters of SoC prototypes were merged to model a target SoC design. The system performance was examined according to the proposed estimation models, the profiling result of the application programs ported on prototypes, and the timing parameters from the post-layout simulation of the target SoC. The experimental result showed that the proposed method was accompanied with only an average of 2.08% of error for an MPEG-4 decoder SoC at simple profile level 2 specifications.
- Subjects
SYSTEMS on a chip; PROTOTYPES; PERFORMANCE evaluation; ESTIMATION theory; HOUSEHOLD electronics design &; construction; INTEGRATED circuit layout
- Publication
VLSI Design, 2013, p1
- ISSN
1065-514X
- Publication type
Article
- DOI
10.1155/2013/529150