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- Title
An Enhanced IEEE1588 Clock Synchronization for Link Delays Based on a System-on-Chip Platform.
- Authors
Xiaohan Wei; Xingzhong Xiong; Zhongqiang Luo; Jianwu Wang; Kaixing Cheng
- Abstract
The clock synchronization is considered as a key technology in the time-sensitive networking (TSN) of 5G fronthaul. This paper proposes a clock synchronization enhancement method to optimize the link delays, in order to improve synchronization accuracy. First, all the synchronization dates are filtered twice to get the good calculation results in the processor, and then FPGA adjust the timer on the slave side to complete clock synchronization. This method is implemented by Xilinx Zynq UltraScale+ MPSoC (multiprocessor system-on-chip), using FPGA+ARM software and hardware co-design platform. The master and slave output Pulse Per-Second signals (PPS). The synchronization accuracy was evaluated by measuring the time offset between PPS signals. Contraposing the TSN, this paper compares the performance of the proposed scheme with some previous methods to show the efficacy of the proposed work. The results show that the slave clock of proposed method is synchronized with the master clock, leading to better robustness and significant improvement in accuracy, with time offset within the range of 40 nanoseconds. This method can be applied to the time synchronization of the 5G open fronthaul network and meets some special service needs in 5G communication.
- Subjects
SYNCHRONIZATION; MULTIPROCESSORS; SYSTEMS on a chip; FIELD programmable gate arrays; 5G networks
- Publication
International Journal of Electronics & Telecommunications, 2021, Vol 67, Issue 2, p289
- ISSN
2081-8491
- Publication type
Article
- DOI
10.24425/ijet.2021.135978