We found a match
Your institution may have access to this item. Find your institution then sign in to continue.
- Title
PARALLELIZATION OF REVERSIBLE RIPPLE-CARRY ADDERS.
- Authors
THOMSEN, MICHAEL KIRKEDAL; AXELSEN, HOLGER BOCK
- Abstract
The design of fast arithmetic logic circuits is an important research topic for reversible and quantum computing. A special challenge in this setting is the computation of standard arithmetical functions without the generation of garbage. Here, we present a novel parallelization scheme wherein m parallel k-bit reversible ripple-carry adders are combined to form a reversible mk-bit ripple-block carry adder with logic depth ${\mathcal O}(m + k)$ for a minimal logic depth ${\mathcal O}(\sqrt {mk} )$, thus improving on the mk-bit ripple-carry adder logic depth ${\mathcal O}(m \cdot k)$. The underlying mechanisms of the parallelization scheme are formally proven correct. We also show designs for garbage-less reversible comparison circuits. We compare the circuit costs of the resulting ripple-block carry adder with known optimized reversible ripple-carry adders in measures of circuit delay, width, gate, transistor count, and relative power efficiency, and find that the parallelized adder offers significant speedups at realistic word sizes with modest parallelization overhead.
- Subjects
COMPUTER arithmetic &; logic units; LOGIC circuits; PARALLEL processing; LOGIC design; TRANSISTORS
- Publication
Parallel Processing Letters, 2009, Vol 19, Issue 2, p205
- ISSN
0129-6264
- Publication type
Article
- DOI
10.1142/S0129626409000171