We found a match
Your institution may have access to this item. Find your institution then sign in to continue.
- Title
An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration.
- Authors
Shyh-Shyuan Sheu; Zhe-Hui Lin; Jui-Feng Hung; Lau, John H.; Peng-Shu Chen; Shih-Hsien Wu; Keng-Li Su; Chih-Sheng Lin; Shinn-Juh Lai; Kuo-Hsing Cheng; Tzu-Kun Ku; Wei-Chung Lo; Ming-Jer Kao
- Abstract
This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV Sparameters, achieves the function of monitoring the SiO2 thickness completeness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.
- Subjects
INTEGRALS; HETEROGENEOUS catalysis; PARASITIC diseases; ELECTRICAL test equipment; BATTERY testers
- Publication
Journal of Microelectronic & Electronic Packaging, 2011, Vol 8, Issue 4, p140
- ISSN
1551-4897
- Publication type
Article
- DOI
10.4071/imaps.307