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- Title
A Fast Lock-In Time, Capacitive FIR-Filter-Based Clock Multiplier with Input Clock Jitter Reduction.
- Authors
Zeng, Zhaoquan; Zhang, Ling; Gong, Lijiao; Zhang, Ning
- Abstract
This paper presents a fast lock-in time clock frequency multiplier without using traditional clock generation circuits such as PLLs and DLLs. We propose a novel technique based on capacitive finite impulse response (FIR) filters to generate clock phases while reducing the input clock phase noise at the same time. A new delay line circuit is also proposed for improving power supply rejection. In addition, to improve the matching quality as well as the end-effects tolerance of the on-chip capacitors, a single-value series/parallel algorithm is proposed. Designed in a 0.18 μ m digital CMOS process, with a 20 MHz input clock frequency, the multiplier achieves a multiplication factor of 5 with a lock-in time of less than 4 clock cycles. The input clock jitter is reduced from 7ns RMS to 153 ps RMS after frequency multiplication.
- Subjects
CLOCKS &; watches; DELAY lines; COMPLEMENTARY metal oxide semiconductors; PARALLEL algorithms; PHASE noise
- Publication
Electronics (2079-9292), 2023, Vol 12, Issue 6, p1439
- ISSN
2079-9292
- Publication type
Article
- DOI
10.3390/electronics12061439