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- Title
Pipeline quantum processor architecture for silicon spin qubits.
- Authors
Patomäki, S. M.; Gonzalez-Zalba, M. F.; Fogarty, M. A.; Cai, Z.; Benjamin, S. C.; Morton, J. J. L.
- Abstract
We propose a quantum processor architecture, the qubit 'pipeline', in which run-time scales additively as functions of circuit depth and run repetitions. Run-time control is applied globally, reducing the complexity of control and interconnect resources. This simplification is achieved by shuttling N-qubit states through a large layered physical array of structures which realise quantum logic gates in stages. Thus, the circuit depth corresponds to the number of layers of structures. Subsequent N-qubit states are 'pipelined' densely through the structures to efficiently wield the physical resources for repeated runs. Pipelining thus lends itself to noisy intermediate-scale quantum (NISQ) applications, such as variational quantum eigensolvers, which require numerous repetitions of the same or similar calculations. We illustrate the architecture by describing a realisation in the naturally high-density and scalable silicon spin qubit platform, which includes a universal gate set of sufficient fidelity under realistic assumptions of qubit variability.
- Subjects
QUANTUM logic; CIRCUIT complexity; QUBITS; QUANTUM gates; QUANTUM computers; LOGIC circuits
- Publication
NPJ Quantum Information, 2024, Vol 10, Issue 1, p1
- ISSN
2056-6387
- Publication type
Article
- DOI
10.1038/s41534-024-00823-y