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- Title
A Bi/Tri-level Self-Adaptive Two-Step DAC Switching Scheme for High-Power Efficiency SAR-Based ADCs.
- Authors
Dong, Siwan; Liu, Changxiang; Bu, Sen; Li, Jiaqi
- Abstract
A high energy-efficient and reference voltage self-adaptive switching scheme for a triple-capacitive array successive approximation register analog-to-digital converters is proposed. The proposed switching time scheme includes Bi-level and Tri-level modes. The operating mode can be automatically switched by the reference voltage self-adaptive module according to the number of reference voltages of the peripheral circuits. The proposed timing scheme has the advantage of automatic compatibility with Bi/Tri-level reference voltage, which can be better adapted to the requirements of different hybrid ADC architectures. In Bi/Tri-level mode, two-step method, and monotonic switching scheme, floating capacitor technology is used to achieving 99.6% and 99.9% savings in average switching energy and a 73.4% reduction in total capacitance compared to the conventional scheme when applied to a 10-bit SAR ADC. The INL and DNL for both the Bi-level reference mode and the Tri-level reference mode are 0.350, 0.347 and 0.177, 0.172, respectively. In addition, the scheme eliminates to reset energy while regulating M to achieve a compromise between energy, area, and linearity. The post-simulation results show that the 10-bit SAR ADC with the proposed switching scheme can achieve a signal-to-noise distortion ratio (SNDR) of 60.53 dB and a spurious-free dynamic range (SFDR) of 68 dB at a sampling rate of 20 MS/s in a 65 nm CMOS process. The area of this ADC is only 0.2392 mm2.
- Subjects
SUCCESSIVE approximation analog-to-digital converters; VOLTAGE references; COMPLEMENTARY metal oxide semiconductors
- Publication
Circuits, Systems & Signal Processing, 2023, Vol 42, Issue 8, p4470
- ISSN
0278-081X
- Publication type
Article
- DOI
10.1007/s00034-023-02352-z