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- Title
ABOUT CACHE ASSOCIATIVITY IN LOW-COST SHARED MEMORY MULTI-MICROPROCESSORS.
- Authors
DRACH, N.; GEFFLAUT, A.; JOUBERT, P.; SEZNEC, A.
- Abstract
Sizes of on-chip caches on current commercial microprocessors range from 16 Kbytes to 36 Kbytes. These microprocessors can be directly used in the design of a low cost single-bus shared memory multiprocessors without using any second-level cache. In this paper, we explore the viability of such a multi-microprocessor. Simulations results clearly establish that performance of such a system will be quite poor if on-chip caches are direct-mapped. On the other hand, when the on-chip caches are partially associative, the achieved level of performance is quite promising. In particular, two recently proposed innovative cache structures, the skewed-associative cache organization and the semi-unified cache organization are shown to work fine.
- Publication
Parallel Processing Letters, 1995, Vol 5, Issue 3, p475
- ISSN
0129-6264
- Publication type
Article
- DOI
10.1142/S0129626495000436