We found a match
Your institution may have access to this item. Find your institution then sign in to continue.
- Title
A Novel Low Power Bitcell Design Featuring Inherent SEU Prevention and Self Correction Capabilities.
- Authors
Chertkow, Oron; Pescovsky, Ariel; Atias, Lior; Fish, Alexander
- Abstract
The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors, and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. The proposed "SEU Hardening Incorporating Extreme Low Power Bitcell Design" (SHIELD) addresses these two major concerns simultaneously. It is based on the concept of gating the conventional cross-coupled inverters while introducing a novel "cut-off" network. This creates redundant storage nodes and eliminates the internal feedback loop during radiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions when operated at a 700mV supply voltage in a 65 nm process. To validate the bitcell's robustness, several test cases and special concerns, including multiple node upsets (MNU) and half-select, are examined.
- Subjects
LOW voltage integrated circuits; RADIATION shielding; BACK up systems; VERY large scale circuit integration; SILICON-on-insulator technology; RADIATION hardening (Electronics)
- Publication
Journal of Low Power Electronics & Applications, 2015, Vol 5, Issue 2, p130
- ISSN
2079-9268
- Publication type
Article
- DOI
10.3390/jlpea5020130