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- Title
Design of a Power-Performance-Area (PPA) Optimized MOS Current Mode Logic Pre-scaler.
- Authors
Maity, Subhanil; Jana, Sanjay Kumar
- Abstract
This work presents a design of a power-performance-area optimized MOS current mode logic pre-scaler. The divide-by-3 pre-scaler is realized in TSMC 180 nm technology node. The post-layout simulation results show that the proposed pre-scaler can operate faithfully up to 10.58 GHz operating frequency in the worst speed corner with a maximum power dissipation of 2.86 mW at the worst power corner. The divider occupies 0.115 × 0.128 mm2 area. The overall performance trade-off presents the figure of merit: FoM of 24 dB, which shows a better trade-off when compared with the state of the art. The impact of PVT variations is also analyzed.
- Subjects
TAIWAN Semiconductor Manufacturing Co. Ltd.; LOGIC; FREQUENCY dividers; WORK design; VOLTAGE-controlled oscillators
- Publication
Circuits, Systems & Signal Processing, 2023, Vol 42, Issue 10, p5783
- ISSN
0278-081X
- Publication type
Article
- DOI
10.1007/s00034-023-02394-3