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- Title
A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits.
- Authors
Wang, Chua-Chin; Hou, Zong-You; Chen, Chih-Lin; Shmilovitz, Doron
- Abstract
This work presents a phase-locked loop (PLL)-based clock and data recovery (CDR) circuit with a lock detector loop to reduce the voltage ripple of voltage-controlled oscillator (VCO). A tunable charge pump is used in this work to adjust the charge current depending on the state of lock detector loop, which is determined by seven clocks with equal phase difference. An experimental prototype is implemented using a typical 0.18-μ<inline-graphic></inline-graphic>m CMOS process to justify the performance. The measurement results reveal that lock detector loop could reduce the voltage amplitude of Vctrl, which is the control of VCO. Notably, the voltage amplitude of Vctrl is reduced 75% from 1 V to 250 mV.
- Subjects
CLOCK &; data recovery circuits; PHASE-locked loops; RIPPLE (Computer network protocol); LOW voltage integrated circuits; ON-chip charge pumps
- Publication
Circuits, Systems & Signal Processing, 2018, Vol 37, Issue 4, p1692
- ISSN
0278-081X
- Publication type
Article
- DOI
10.1007/s00034-017-0621-7