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- Title
11 b 200 MS/s 28-nm CMOS 2b/cycle successive-approximation register analogue-to-digital converter using offset-mismatch calibrated comparators.
- Authors
Jaehyuk Lee; Junho Boo; Junsang Park; Taiji An; Heewook Shin; Youngjae Cho; Choi, Michael; Jinwook Burm; Gilcho Ahn; Seunghoon Lee
- Abstract
This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive-approximation register (SAR) analogue-to-digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of the high-resolution 2b/cycle SAR ADC. The offset mismatch is reduced to within 0.25 least significant bit (LSB) by generating a compensation voltage from capacitor-resistor (C-R) hybrid digital-to-analogue converters (DACs). The prototype ADC implemented in a 28-nm CMOS process demonstrates measured differential and integral non-linearities within 0.6 LSB and 1.73 LSB at 11 b resolution, respectively. The measured signal-to-noise-and-distortion ratio (SNDR) and spuriousfree dynamic range (SFDR) are 50.9 dB and 66.2 dB at Nyquist, respectively. The prototype ADC occupies an active die area of 0.115 mm² and consumes 3.98 mW at a 1.1-V supply voltage.
- Subjects
SUCCESSIVE approximation analog-to-digital converters; COMPARATOR circuits; COMPLEMENTARY metal oxide semiconductors; ON-chip charge pumps; VOLTAGE; VOLTAGE-controlled oscillators
- Publication
Electronics Letters (Wiley-Blackwell), 2023, Vol 59, Issue 16, p1
- ISSN
0013-5194
- Publication type
Article
- DOI
10.1049/ell2.12929