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MODELLING AND ESTIMATION OF WAFER YIELDS AND DEFECT DENSITIES FROM MICROELECTRONICS TEST STRUCTURE DATA.
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- Quality & Reliability Engineering International, 1996, v. 12, n. 1, p. 9, doi. 10.1002/(SICI)1099-1638(199601)12:1<9::AID-QRE975>3.0.CO;2-K
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- Article
Electronic Packaging Reliability Assessment.
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- Quality & Reliability Engineering International, 1991, v. 7, n. 1, p. 50
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- Article
De-embedding techniques for embedded microstrips.
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- Microwave & Optical Technology Letters, 2004, v. 42, n. 1, p. 50, doi. 10.1002/mop.20204
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- Article
Matching characteristics of high-performance, low-cost, analog fiber-optic links for arrayed-antenna applications.
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- Microwave & Optical Technology Letters, 2000, v. 24, n. 6, p. 363, doi. 10.1002/(SICI)1098-2760(20000320)24:6<363::AID-MOP1>3.0.CO;2-O
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- Article
Design of due-date oriented look-ahead batching rule in wafer fabrication.
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- International Journal of Advanced Manufacturing Technology, 2007, v. 35, n. 5/6, p. 596, doi. 10.1007/s00170-006-0723-z
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- Article
A hybrid look-ahead SOM-FBPN and FIR system for wafer-lot-output time prediction and achievability evaluation.
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- International Journal of Advanced Manufacturing Technology, 2007, v. 35, n. 5/6, p. 575, doi. 10.1007/s00170-006-0741-x
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- Article
Development of a new cluster index for wafer defects.
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- International Journal of Advanced Manufacturing Technology, 2006, v. 31, n. 7/8, p. 705, doi. 10.1007/s00170-005-0240-5
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- Article
Stress analysis of lead-free solders with under bump metallurgy in a wafer level chip scale package.
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- International Journal of Advanced Manufacturing Technology, 2006, v. 31, n. 1/2, p. 1, doi. 10.1007/s00170-005-0165-z
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- Article
A new VLSI implementation of additive synthesis.
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- Computer Music Journal, 1998, v. 22, n. 3, p. 49, doi. 10.2307/3681157
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Wetting-Assisted Crack- and Wrinkle-Free Transfer of Wafer-Scale Graphene onto Arbitrary Substrates over a Wide Range of Surface Energies.
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- Advanced Functional Materials, 2016, v. 26, n. 13, p. 2070, doi. 10.1002/adfm.201504551
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- Article
A Dynamic TNFS Rule for Job Dispatching in a Wafer Fab.
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- International Review on Computers & Software, 2011, v. 6, n. 3, p. 412
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- Article
The SOM-RBF Approach for Forecasting Job Interval Cycle Time in a Wafer Fab.
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- International Review on Computers & Software, 2011, v. 6, n. 3, p. 407
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- Article
Optimizing Cycle Time Average and Variation for a Wafer Fabrication Factory with a Dynamic Dispatching Rule.
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- International Review on Computers & Software, 2011, v. 6, n. 3, p. 400
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- Article
Thin Film Transistors Using Wafer-Scale Low-Temperature MOCVD WSe.
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- Journal of Electronic Materials, 2016, v. 45, n. 12, p. 6280, doi. 10.1007/s11664-016-4987-2
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- Article
Improvement of Thermal Fatigue Properties of Sn-Ag-Cu Lead-Free Solder Interconnects on Casio’s Wafer-Level Packages Based on Morphology and Grain Boundary Character.
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- Journal of Electronic Materials, 2009, v. 38, n. 1, p. 33, doi. 10.1007/s11664-008-0560-y
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- Article
Three-step approach for wafer sawing lane inspection.
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- Optical Engineering, 2009, v. 48, n. 11, p. 117204, doi. 10.1117/1.3265714
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- Article
Versatile pattern generation of periodic, high aspect ratio Si nanostructure arrays with sub-50-nm resolution on a wafer scale.
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- Nanoscale Research Letters, 2013, v. 8, n. 1, p. 1, doi. 10.1186/1556-276X-8-506
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SMARTIEHS Offers Faster Inspection of Micro-Optical Components.
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- Electronic Device Failure Analysis, 2011, v. 13, n. 2, p. 41
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- Article
Electroglas Offers Advanced Dual-Loops Z-Stage Control.
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- Electronic Device Failure Analysis, 2008, v. 10, n. 3, p. 42
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- Article
A “thru-short” method for noise de-embedding of MOSFETs.
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- Microwave & Optical Technology Letters, 2009, v. 51, n. 5, p. 1379, doi. 10.1002/mop.24330
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Self-Aligned Wafer-Level Integration Technology with an embedded faraday cage for substrate crosstalk suppression.
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- Microwave & Optical Technology Letters, 2008, v. 50, n. 3, p. 829, doi. 10.1002/mop.23207
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- Article
DEVELOPMENT OF A DUAL BURN-IN POLICY FOR SEMICONDUCTOR PRODUCTS BASED ON THE NUMBER OF DEFECTIVE NEIGHBORHOOD CHIPS.
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- International Journal of Reliability, Quality & Safety Engineering, 2006, v. 13, n. 6, p. 501, doi. 10.1142/S0218539306002409
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Modeling of the MEMS Reactive Ion Etching Process Using Neural Networks.
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- Jordan Journal of Mechanical & Industrial Engineering, 2011, v. 5, n. 4, p. 353
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WLBI and Test Churn Out KGD.
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- EE: Evaluation Engineering, 2008, v. 47, n. 2, p. 42
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Testing MEMS at Wafer Level.
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- EE: Evaluation Engineering, 2004, v. 43, n. 9, p. 20
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- Article
Controlling Contact Resistance.
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- EE: Evaluation Engineering, 2004, v. 43, n. 5, p. 56
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Screen-printed single-walled carbon nanotube networks and their use for dimethyl methylphosphonate detection.
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- Journal of Materials Science: Materials in Electronics, 2012, v. 23, n. 10, p. 1823, doi. 10.1007/s10854-012-0669-x
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- Article
Innovative methodologies of circuit edit by focused ion beam (FIB) on wafer-level chip-scale-package (WLCSP) devices.
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- Journal of Materials Science: Materials in Electronics, 2011, v. 22, n. 10, p. 1536, doi. 10.1007/s10854-011-0457-z
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- Article
A mixed elastohydrodynamic lubrication model for simulation of chemical mechanical polishing with double-layer structure of polishing pad.
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- International Journal of Advanced Manufacturing Technology, 2015, v. 77, n. 1-4, p. 107, doi. 10.1007/s00170-014-6438-7
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Pursuing efficiency from wafer to system.
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- EE: Evaluation Engineering, 2015, v. 54, n. 8, p. 16
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Wafer‐Scale Nanoimprint Lithography Process Towards Complementary Silicon Nanowire Field‐Effect Transistors for Biosensor Applications.
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- Physica Status Solidi. A: Applications & Materials Science, 2018, v. 215, n. 15, p. 1, doi. 10.1002/pssa.201800234
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Future bright with copper, low-k, 300mm, shrink.
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- Solid State Technology, 2001, v. 44, n. 9, p. 20
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First wafer-scale packages show up in commercial products.
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- Solid State Technology, 2000, v. 43, n. 10, p. 39
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TI plans DMOS 4 upgrade.
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- Solid State Technology, 1999, v. 42, n. 7, p. 40
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Wafer-level packaging technology milestones.
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- Solid State Technology, 1998, v. 41, n. 10, p. 42
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Modeling and Parameter Extraction of Test Fixtures for MOSFET On-Wafer Measurements up to 60 GHz.
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- International Journal of RF & Microwave Computer-Aided Engineering, 2013, v. 23, n. 6, p. 655, doi. 10.1002/mmce.20701
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High-mobility three-atom-thick semiconducting films with wafer-scale homogeneity.
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- Nature, 2015, v. 520, n. 7549, p. 656, doi. 10.1038/nature14417
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Experimental characterization of wafer probe burn.
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- Turkish Journal of Electrical Engineering & Computer Sciences, 2016, v. 24, n. 5, p. 3513, doi. 10.3906/elk-1407-109
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Precise Patterning of Large‐Scale TFT Arrays Based on Solution‐Processed Oxide Semiconductors: A Comparative Study of Additive and Subtractive Approaches.
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- Advanced Materials Interfaces, 2018, v. 5, n. 1, p. 1, doi. 10.1002/admi.201700981
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Wafer Scale Solventless Adhesive Bonding with iCVD Polyglycidylmethacrylate: Effects of Bonding Parameters on Adhesion Energies.
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- Advanced Materials Interfaces, 2015, v. 2, n. 9, p. n/a, doi. 10.1002/admi.201500076
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Graphene/Si-nanowire heterostructure molecular sensors.
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- Scientific Reports, 2014, p. 1, doi. 10.1038/srep05384
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Ultrafast perturbation maps as a quantitative tool for testing of multi-port photonic devices.
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- Nature Communications, 2018, v. 9, n. 1, p. 1, doi. 10.1038/s41467-018-04662-2
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Simple, Fast, and Cost-Effective Fabrication of Wafer-Scale Nanohole Arrays on Silicon for Antireflection.
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- Journal of Nanomaterials, 2014, p. 1, doi. 10.1155/2014/439212
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Current tuned slotted Y‐branch laser for wafer thickness measurements with THz radiation.
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- Electronics Letters (Wiley-Blackwell), 2021, v. 57, n. 24, p. 936, doi. 10.1049/ell2.12314
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Wafer-scale integration of group III-V lasers on silicon using transfer printing of epitaxial layers.
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- Nature Photonics, 2012, v. 6, n. 9, p. 612, doi. 10.1038/nphoton.2012.204
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