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- Title
Identifying transistor-level yield limiters in the FinFET era.
- Authors
Eide, Geir
- Abstract
The article discusses several aspects of identifying transistor-level limiters through the Fin Field Effect Transistor (FinFET). It mentions the technology to perform transistor-level diagnosis, called cell-aware diagnosis, can identify both static and timing-sensitive defects inside standard cells. It also mentions the cell-aware diagnosis works for any scan automatic test pattern generation (ATPG) pattern type, such as stuck-at, transition- delay, and cell-aware.
- Subjects
LIMITER circuits; TRANSISTORS; STANDARD cells; AUTOMATIC test pattern generation; ELECTRONIC circuits
- Publication
EE: Evaluation Engineering, 2017, Vol 56, Issue 5, p18
- ISSN
0149-0370
- Publication type
Article