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- Title
Rapid Prototyping of the Data-Driven Chip-Multiprocessor (D<sup>2</sup>-CMP) using FPGAs.
- Authors
Tatas, Konstantinos; Kyriacou, Costas; Evripidou, Paraskevas; Trancoso, Pedro; Wong, Stephan
- Abstract
This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that enables thread execution using dataflow-like scheduling policy on a chip multiprocessor. Threads are scheduled for execution based on data availability, i.e., a thread is scheduled for execution only if its input data is available. This model of execution is called the non-blocking Data-Driven Multithreading (DDM) model of execution. The DDM model has been evaluated using an execution driven simulator. To validate the simulation results, a 2-node DDM chip multiprocessor has been implemented on a Xilinx Virtex-II Pro FPGA with two PowerPC processors hardwired on the FPGA. Measurements on the hardware prototype show that the TSU can be implemented with a moderate hardware budget. The 2-node multiprocessor has been implemented with less than half of the reconfigurable hardware available on the Xilinx Virtex-II Pro FPGA (45% slices), which corresponds to an ASIC equivalent gate count of 1.9 million gates. Measurements on the prototype showed that the delays incurred by the operation of the TSU can be tolerated.
- Subjects
RAPID prototyping; PARALLEL processing; ELECTRONIC data processing; MULTIPROCESSORS; THREADS (Computer programs)
- Publication
Parallel Processing Letters, 2008, Vol 18, Issue 2, p291
- ISSN
0129-6264
- Publication type
Article
- DOI
10.1142/S0129626408003399