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- Title
Technique for multi-core instruction-set simulator.
- Authors
LUO Han-qing; LIANG Li-ping; YE Tian-chun
- Abstract
In order to improve the simulation speed of multi-core instruction-set simulator (ISS) with low complexity, this paper presented a technique, which combined the advantages of interpretive strategy and compiled strategy, to form a multi-core ISS quickly. This technique used pre-decoder technique, extendable single core structure, cache and TLB simulation in single core, and the multi-core scheduling compatibly. This technique had been applied on forming multi-core simulator ISD, which was based on IME-diamond multi-core DSP processor. Complexity analysis and the experiment results show that this technique improves the simulation speed with low complexity.
- Subjects
SET theory; COMPUTATIONAL complexity; SIMULATION methods &; models; DECODERS &; decoding; COMPUTER systems
- Publication
Application Research of Computers / Jisuanji Yingyong Yanjiu, 2013, Vol 30, Issue 10, p3035
- ISSN
1001-3695
- Publication type
Article
- DOI
10.3969/j.issn.1001-3695.2013.10.036