We found a match
Your institution may have access to this item. Find your institution then sign in to continue.
- Title
Voltage Controlled Ring Oscillator with Phase Compensation Technique for Jitter Reduction in 180 nm CMOS Technology.
- Authors
Mishra, Abhishek; Singh, Anil; Agarwal, Alpana
- Abstract
This paper presents a novel jitter reduction technique for a voltage-controlled ring oscillator (VCRO). This technique is helpful in employing VCRO-based circuits like Analog to Digital Converter (ADC), Phase Locked Loop (PLL) and time-based circuits whose performance is severely degraded by high jitter. In the proposed technique, the jitter is extracted using Excess Phase Discrimination (EPD) block and is transformed into Pulse Width Modulated (PWM) signal, which is then fed into the Phase Compensator (PC) block. This block reduces the jitter by about half its value after enabling the Single Ended Injection Locking (SEIL). The proposed work is designed in SCL 180 nm CMOS technology at 1.8 V supply. On enabling the proposed circuit, the Root Mean Square (RMS) jitter reduces from 5.94 to 2.58 ps (about 56%) for VCRO running at 58 MHz and consumes a total power of 375.84 μ W. The overall performance of the proposed circuit does not vary much in the post-layout simulations, hence demonstrating the effectiveness of the proposed technique.
- Subjects
ANALOG-to-digital converters; PHASE-locked loops; DIGITAL-to-analog converters; ANALOG circuits; ROOT-mean-squares; VOLTAGE-controlled oscillators; FREQUENCY synthesizers
- Publication
Journal of Circuits, Systems & Computers, 2024, Vol 33, Issue 8, p1
- ISSN
0218-1266
- Publication type
Article
- DOI
10.1142/S0218126624501433